# US 10,483,390 B2 · Insulated gate semiconductor device and method of manufacturing same

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- Number: US 10,483,390 B2
- Document ID: US10483390B2
- Status: Granted
- Kind: B2
- Application number: 15/973,921
- Filed: 2018-05-08
- Published: 2018-12-06
- Granted: 2019-11-19
- Earliest claimed: 2017-06-02
- Assignees: Fuji Electric Co., Ltd.
- Applicants: Fuji Electric Co., Ltd.
- Inventors: Keiji Okumura
- Web page: https://patentgrep.com/patent/US10483390B2

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 12/031: {of IGBTs}
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/125: {Shapes of junctions between the regions}
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D 62/364: {of IGFETs}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/8325: {Silicon carbide}
- H10D 64/281: {Base electrodes for bipolar transistors}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10P 30/2042: {into crystalline silicon carbide}
- H10P 30/21: {of electrically active species}
- H10P 30/22: using masks
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10D 18/655: {produced by insulated gate structures}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An insulated gate semiconductor device includes p+ gate bottom protection regions embedded in a drift layer at the bottoms of trenches that goes through n+ source regions and p-type base regions, and p+ base bottom embedded regions embedded in the drift layer below the base regions. The base bottom embedded regions have trapezoidal shapes due to a channeling phenomenon, and the bottom surfaces of the base bottom embedded regions are deeper than the bottom surfaces of the gate bottom protection regions.

## Claims

### Claim 1

An insulated gate semiconductor device, comprising:
a drift layer of a first conductivity type made of a semiconductor material having a wider bandgap than silicon, a top surface of the semiconductor material having an off-angle;
a base region of a second conductivity type made of said semiconductor material, disposed above the drift layer;
a first high-impurity region of the first conductivity type, embedded in a top of the base region and having a higher impurity density than the drift layer, wherein a trench is provided penetrating the first high-impurity region and the base region;
a gate insulating film disposed on side surfaces and a bottom surface of the trench;
an embedded gate electrode embedded inside the trench, with the gate insulating film being interposed between the trench and the embedded gate electrode;
a second high-impurity region of the first conductivity type made of said semiconductor material, disposed on a bottom surface side of the drift layer;
a gate bottom protection region of the second conductivity type, embedded in the drift layer at a bottom of the trench; and
a base bottom embedded region of the second conductivity type, embedded in the drift layer below the base region separately from the gate bottom protection region, and having a higher impurity density than the base region,
wherein a cross-section of the base bottom embedded region has a trapezoid-shaped portion on at least a bottom side of the base bottom embedded region, an upper base and a lower base of the trapezoid are parallel, and a virtual straight line that connects a midpoint of the upper base and a midpoint of the lower base is tilted from a line normal to the top surface of the drift layer towards a direction of the off-angle by a prescribed tilt angle, and
wherein a bottom surface of the base bottom embedded region is deeper than a bottom surface of the gate bottom protection region.

### Claim 2 (depends on 1)

The insulated gate semiconductor device according to claim 1, wherein the tilt angle is within ±3° measured in the direction of the off-angle relative to the c-axis direction of a crystal forming the drift layer.

### Claim 3 (depends on 1)

The insulated gate semiconductor device according to claim 1, wherein the bottom surface of the base bottom embedded region is at least 0.1 μm deeper than the bottom surface of the gate bottom protection region.

### Claim 4 (depends on 1)

The insulated gate semiconductor device according to any one of claims 1, wherein the base bottom embedded region comprises:
a first embedded region; and
a second embedded region disposed above the first embedded region.

### Claim 5 (depends on 1)

The insulated gate semiconductor device according to claim 1, further comprising:
a base contact plug penetrating the first high-impurity region and the base region and reaching and being in contact with the base bottom embedded region.

### Claim 6 (depends on 5)

The insulated gate semiconductor device according to claim 5, wherein a side wall of the base contact plug is parallel to a side surface of the base bottom embedded region.

### Claim 7 (depends on 1)

The insulated gate semiconductor device according to claim 1, wherein the semiconductor material is silicon carbide.

### Claim 8 (depends on 1)

The insulated gate semiconductor device according to claim 1, wherein the o off-angle is greater than 3° and is less than or equal to 8°.

### Claim 9 (depends on 1)

The insulated gate semiconductor device according to claim 1,
wherein the drift layer includes a current spreading layer of the first conductivity type in an upper layer of the drift layer, the current spreading layer having a higher impurity concentration than a rest of the drift layer, and
wherein the gate bottom protection region and the base bottom embedded region are both embedded in the current spreading layer in the drift layer.

### Claim 10 (depends on 1)

The insulated gate semiconductor device according to claim 1, wherein the off-angle is greater than 3° and less than or equal to 8°, and the tilt angle is nonzero and within ±3° of the off-angle.