# US 10,483,389 B2 · Silicon carbide semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,389 B2 - Document ID: US10483389B2 - Status: Granted - Kind: B2 - Application number: 14/968,430 - Filed: 2015-12-14 - Published: 2016-04-21 - Granted: 2019-11-19 - Earliest claimed: 2014-07-02 - Assignees: Hestia Power Inc. - Applicants: Hestia Power Inc. - Inventors: Cheng-Tyng Yen; Chien-Chung Hung; Chwan-Ying Lee; Lurng-Shehng Lee - Web page: https://patentgrep.com/patent/US10483389B2 ## CPC - H10D 84/146: {the built-in components being Schottky barrier diodes} - H10D 30/662: {having a drift region having a doping concentration that is higher between adjacent body regions relative to other parts of the drift region} - H10D 62/10: Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies - H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions} - H10D 62/125: {Shapes of junctions between the regions} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 62/8325: {Silicon carbide} - H10D 64/519: {characterised by their top-view geometrical layouts} - H10D 8/60: Schottky-barrier diodes - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 64/62: Electrodes ohmically coupled to a semiconductor - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly connected Schottky diode includes: an n-type substrate, an n-type drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an inter-layer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer. The second metal layer at the junction openings forms the Schottky diode. ## Claims ### Claim 1 A silicon carbide (SiC) semiconductor device, comprising: an n-type substrate, having a first doping concentration; an n-type drift layer, disposed on the n-type substrate, having a second doping concentration less than the first doping concentration; a plurality of doped regions, disposed at the n-type drift layer, spaced from each other and formed a plurality of junction field effect transistor (JFET) regions, each of the JFET regions having a third doping concentration therebetween, each of the doped regions comprising a p-well, a heavily doped n-type (n+) region located in the p-well, and a heavily doped p-type (p+) region; a gate dielectric layer, disposed on the n-type drift layer; a gate electrode, disposed on the gate dielectric layer; an inter-layer dielectric layer, disposed on the gate dielectric layer and the gate electrode; a plurality of source openings, penetrating through the inter-layer dielectric layer and the gate dielectric layer to a surface portion of the heavily doped n+ region and the heavily doped p+ region, and the plurality of source openings are separated by the gate electrode and the inter-layer dielectric layer, wherein a top surface of n-type drift layer and a top surface of the heavily doped p+ region are in a same first plane; a plurality of junction openings, penetrating through the inter-layer dielectric layer and the gate dielectric layer to a surface portion of the plurality of JFET regions and the doped regions, and the plurality of junction openings are separated by the gate electrode and the inter-layer dielectric layer; a plurality of gate openings, penetrating through the inter-layer dielectric layer to a surface portion of the gate electrode; a first metal layer, disposed only at a bottom of the source openings, formed an Ohmic contact with the surface portion of the heavily doped n+ region and the heavily doped p+ region; a second metal layer, comprising a first portion and a second portion, wherein the first portion covers the source openings and the junction openings, is electrically connected to the first metal layer, and forms a Schottky contact with the surface portion of the plurality of JFET regions, the second portion covers the gate openings and is electrically insulated from the first portion, wherein a bottom surface of the first metal layer and a bottom surface of a part of the second metal layer are in a same second plane; and wherein the third doping concentration is greater than the second doping concentration. ### Claim 2 (depends on 1) The SiC semiconductor device of claim 1, wherein the plurality of JFET regions having a first depth, the p-well having a second depth, the heavily doped n+ region having a third depth, the heavily doped p+ regions having a fourth depth, wherein the second depth is greater than the third depth. ### Claim 3 (depends on 2) The SiC semiconductor device of claim 2, wherein the first depth is greater than or equal to the second depth. ### Claim 4 (depends on 2) The SiC semiconductor device of claim 2, wherein the first depth is greater than or equal to the fourth depth. ### Claim 5 (depends on 1) The SiC semiconductor device of claim 1, wherein the heavily doped p+ region is surrounded by the p-well and the heavily doped n+ region, and at least a portion of the heavily doped p+ region overlaps with the p-well. ### Claim 6 (depends on 1) The SiC semiconductor device of claim 1, wherein the substrate is a 4H-SiC substrate. ### Claim 7 (depends on 1) The SiC semiconductor device of claim 1, wherein the first metal layer comprising a silicide or a combination of silicides of a material selected from a group consisting of nickel, titanium, aluminum, molybdenum and niobium. ### Claim 8 (depends on 1) The SiC semiconductor device of claim 1, wherein the second metal layer is selected from a group or a combination consisting of titanium, molybdenum, nickel, aluminum, titanium silicide, molybdenum silicide, nickel silicide, aluminum silicide, titanium nitride, an aluminum copper alloy and an aluminum silicon copper alloy. ### Claim 9 (depends on 1) The SiC semiconductor device of claim 1, wherein a planar contour of the p-well is selected from a group consisting of a square, a rectangle, a hexagon and a long stripe. ### Claim 10 (depends on 1) The SiC semiconductor device of claim 1, wherein a planar contour of the source openings is selected from a group consisting of a quadrilateral, a hexagon, an octagon, a circle and a long stripe. ### Claim 11 (depends on 1) The SiC semiconductor device of claim 1, wherein a planar contour of the junction openings is selected from a group consisting of a quadrilateral, a hexagon, an octagon, a circle and a long stripe. ### Claim 12 A silicon carbide (SiC) semiconductor device, comprising: an n-type substrate, having a first doping concentration; an n-type drift layer, disposed on the substrate, having a second doping concentration less than the first doping concentration; a plurality of first doped regions and a plurality of second doped regions, disposed at the n-type drift layer, each of the first doped regions comprising a first p-well, a heavily doped n-type (n+) region located in the first p-well, and a first heavily doped p-type (p+) region located in the first p-well and surrounded by the heavily doped n+ region, each of the second doped regions comprising at least one sub-doped region, wherein each of a plurality of first junction field effect transistor (JFET) regions having a third doping concentration formed between each of the first doped regions and the second doped regions, and each of a plurality of second junction field effect transistor (JFET) regions having a fourth doping concentration formed between each of the sub-doped regions or enclosed by the sub-doped region; a gate dielectric layer, disposed on the n-type drift layer; a gate electrode, disposed on the gate dielectric layer; an inter-layer dielectric layer, disposed on the gate dielectric layer and the gate electrode; a plurality of source openings, penetrating through the inter-layer dielectric layer and the gate dielectric layer to a surface portion of the heavily doped n+ region and the first heavily doped p+ region, and the plurality of source openings are separated by the gate electrode and the inter-layer dielectric layer, wherein a top surface of n-type drift layer and a top surface of the heavily doped p+ region are in a same first plane; a plurality of junction openings, penetrating through the inter-layer dielectric layer and the gate dielectric layer to a surface portion of the plurality of second JFET regions and the second doped regions, and the plurality of junction openings are separated by the gate electrode and the inter-layer dielectric layer; a plurality of gate openings, penetrating through the inter-layer dielectric layer to a surface portion of the gate electrode; a first metal layer, disposed only at a bottom of the source openings, formed an Ohmic contact with the surface portion of the heavily doped n+region and the first heavily doped p+ region; a second metal layer, comprising a first portion and a second portion, wherein the first portion covers the source openings and the junction openings, is electrically connected to the first metal layer, and forms a Schottky contact with the surface portion of the plurality of second JFET regions, the second portion covers the gate openings and is electrically insulated from the first portion, wherein a bottom surface of the first metal layer and a bottom surface of a part of the second metal layer are in a same second plane, and wherein the third doping concentration is greater than the second doping concentration. ### Claim 13 (depends on 12) The SiC semiconductor device of claim 12, wherein the sub-doped region is selected from a group consisted of a second p-well, a second heavily doped p-type (p+) region and the combination thereof. ### Claim 14 (depends on 12) The SiC semiconductor device of claim 12, wherein the plurality of first JFET regions having a first depth, the p-well having a second depth, the heavily doped n+ region having a third depth, the heavily doped p+ region having a fourth depth, wherein the second depth is greater than the third depth. ### Claim 15 (depends on 14) The SiC semiconductor device of claim 14, wherein the first depth is greater than or equal to the second depth. ### Claim 16 (depends on 14) The SiC semiconductor device of claim 14, wherein the first depth is greater than or equal to the fourth depth. ### Claim 17 (depends on 12) The SiC semiconductor device of claim 12, wherein the first heavily doped p+ region is surrounded by the first p-well and the heavily doped n+ region, and at least a portion of the first heavily doped p+ region overlaps with the first p-well. ### Claim 18 (depends on 12) The SiC semiconductor device of claim 12, wherein the substrate is a 4H-SiC substrate. ### Claim 19 (depends on 12) The SiC semiconductor device of claim 12, wherein the first metal layer comprising a silicide or a combination of silicides of a material selected from a group consisting of nickel, titanium, aluminum, molybdenum and niobium. ### Claim 20 (depends on 12) The SiC semiconductor device of claim 12, wherein the second metal layer is selected from a group or a combination consisting of titanium, molybdenum, nickel, aluminum, titanium silicide, molybdenum silicide, nickel silicide, aluminum silicide, titanium nitride, an aluminum copper alloy and an aluminum silicon copper alloy. ### Claim 21 (depends on 12) The SiC semiconductor device of claim 12, wherein a planar contour of the first p-well and the sub-doped region are selected from a group consisting of a square, a rectangle, a hexagon and a long stripe. ### Claim 22 (depends on 12) The SiC semiconductor device of claim 12, wherein a planar contour of the source openings is selected from a group consisting of a quadrilateral, a hexagon, an octagon, a circle and a long stripe. ### Claim 23 (depends on 12) The SiC semiconductor device of claim 12, wherein a planar contour of the junction openings is selected from a group consisting of a quadrilateral, a hexagon, an octagon, a circle and a long stripe.