# US 10,483,385 B2 · Nanowire structures having wrap-around contacts

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,483,385 B2
- Document ID: US10483385B2
- Status: Granted
- Kind: B2
- Application number: 13/995,914
- Filed: 2011-12-23
- Published: 2014-07-31
- Granted: 2019-11-19
- Earliest claimed: 2011-12-23
- Assignees: Intel Corporation
- Applicants: Stephen M. Cea; Cory E. Weber; Patrick H. Keys; Seiyon Kim; Michael G. Haverty; Sadasivan Shankar
- Inventors: Stephen M. Cea; Cory E. Weber; Patrick H. Keys; Seiyon Kim; Michael G. Haverty; Sadasivan Shankar
- Web page: https://patentgrep.com/patent/US10483385B2

## CPC

- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/0191: {forming stacked channels, e.g. changing their shapes or sizes}
- H10D 30/502: {characterised by the stacked channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- B82Y 40/00: Manufacture or treatment of nanostructures
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.

## Claims

### Claim 1

A nanowire semiconductor device, comprising:
a nanowire disposed above a substrate;
a channel region disposed in the nanowire, the channel region having a length and a perimeter orthogonal to the length, wherein the perimeter of the channel region is a smallest perimeter of the nanowire;
a gate electrode stack surrounding the entire perimeter of the channel region;
a pair of source and drain regions disposed in the nanowire, on either side of the channel region, each of the source and drain regions having a perimeter orthogonal to the length of the channel region, wherein the perimeters of the source and drain regions are approximately the same, and are greater than the perimeter of the channel region at locations immediately adjacent the channel region, and wherein the smallest perimeter of the nanowire is at the locations where the source and drain regions are immediately adjacent the channel region;
a pair of conductive contacts, a first of the pair of conductive contacts completely surrounding and in contact with the entire perimeter of the source region, and a second of the pair of conductive contacts completely surrounding and in contact with the entire perimeter of the drain region, wherein the pair of conductive contacts has an uppermost surface co-planar with an uppermost surface of the gate electrode stack;
a pair of spacers disposed between the gate electrode stack and the pair of conductive contacts; and
an intervening semiconductor material below and in contact with the nanowire but not along sidewalls of the nanowire at a location beneath the pair of spacers.

### Claim 2 (depends on 1)

The nanowire semiconductor device of claim 1, wherein the channel region has a width and a height, the width approximately the same as the height, and wherein each of the source and drain regions has a width and a height, the width approximately the same as the height.

### Claim 3 (depends on 1)

The nanowire semiconductor device of claim 1, wherein the nanowire consists essentially of silicon, and the entire perimeter of each of the source and drain regions is an exposed <111> silicon surface.

### Claim 4 (depends on 1)

The nanowire semiconductor device of claim 1, further comprising:
a doping layer disposed on and completely surrounding the perimeter of each of the source and drain regions, between the source and drain regions and the pair of conductive contacts.

### Claim 5 (depends on 1)

The nanowire semiconductor device of claim 1, wherein the gate electrode stack comprises a metal gate and a high-K gate dielectric, and the nanowire comprises silicon, germanium, or a combination thereof.

### Claim 6 (depends on 1)

The nanowire semiconductor device of claim 1, wherein the channel region has a width and a height, the width substantially greater than the height, and wherein each of the source and drain regions has a width and a height, the width substantially greater than the height.

### Claim 7 (depends on 6)

The nanowire semiconductor device of claim 6, wherein the nanowire consists essentially of silicon, the perimeter along the width of each of the source and drain regions comprises exposed <110> silicon surfaces, and the perimeter along the height of each of the source and drain regions comprises exposed <100> silicon surfaces.

### Claim 8 (depends on 1)

The nanowire semiconductor device of claim 1, wherein the channel region has a width and a height, the width substantially less than the height, and wherein each of the source and drain regions has a width and a height, the width substantially less than the height.

### Claim 9 (depends on 8)

The nanowire semiconductor device of claim 8, wherein the nanowire consists essentially of silicon, the perimeter along the width of each of the source and drain regions comprises exposed <100> silicon surfaces, and the perimeter along the height of each of the source and drain regions comprises exposed <110> silicon surfaces.

### Claim 10

A semiconductor device, comprising:
a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising:
a discrete channel region disposed in the nanowire, the channel region having a length and a perimeter orthogonal to the length, wherein the perimeter of the channel region is a smallest perimeter of the nanowire;
a pair of discrete source and drain regions disposed in the nanowire, on either side of the channel region, each of the source and drain regions having a perimeter orthogonal to the length of the channel region, wherein the perimeters of the source and drain regions are approximately the same, and are greater than the perimeter of the channel region at locations immediately adjacent the channel region, and wherein the smallest perimeter of the nanowire is at the locations where the source and drain regions are immediately adjacent the channel region;
a gate electrode stack surrounding and in contact with the entire perimeter of each of the channel regions;
a pair of conductive contacts, a first of the pair of conductive contacts completely surrounding the perimeter of each of the source regions, and a second of the pair of conductive contacts completely surrounding and in contact with the entire perimeter of each of the drain regions, wherein the pair of conductive contacts has an uppermost surface co-planar with an uppermost surface of the gate electrode stack;
a pair of spacers disposed between the gate electrode stack and the pair of conductive contacts; and
an intervening semiconductor material between and in contact with the plurality of vertically stacked nanowires but not along sidewalls of the nanowires at a location beneath the pair of spacers.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein each of the channel regions has a width and a height, the width approximately the same as the height, and wherein each of the source and drain regions has a width and a height, the width approximately the same as the height.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein each of the nanowires consists essentially of silicon, and the entire perimeter of each of the source and drain regions is an exposed <111> silicon surface.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, further comprising:
a doping layer disposed on and completely surrounding the perimeter of each of the source and drain regions, between the source and drain regions and the pair of conductive contacts.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, wherein the gate electrode stack comprises a metal gate and a high-K gate dielectric, and each of the nanowires comprises silicon, germanium, or a combination thereof.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, wherein each of the channel regions has a width and a height, the width substantially greater than the height, and wherein each of the source and drain regions has a width and a height, the width substantially greater than the height.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein each of the nanowires consists essentially of silicon, the perimeter along the width of each of the source and drain regions comprises exposed <110> silicon surfaces, and the perimeter along the height of each of the source and drain regions comprises exposed <100> silicon surfaces.

### Claim 17 (depends on 10)

The semiconductor device of claim 10, wherein each of the channel regions has a width and a height, the width substantially less than the height, and wherein each of the source and drain regions has a width and a height, the width substantially less than the height.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein each of the nanowires consists essentially of silicon, the perimeter along the width of each of the source and drain regions comprises exposed <100> silicon surfaces, and the perimeter along the height of each of the source and drain regions comprises exposed <110> silicon surfaces.

### Claim 19

A method of fabricating a nanowire semiconductor device, the method comprising:
forming a nanowire above a substrate;
forming a channel region in the nanowire, the channel region having a length and a perimeter orthogonal to the length, wherein the perimeter of the channel region is a smallest perimeter of the nanowire;
forming a gate electrode stack surrounding the entire perimeter of the channel region;
forming a pair of source and drain regions in the nanowire, on either side of the channel region, each of the source and drain regions having a perimeter orthogonal to the length of the channel region, wherein the perimeters of the source and drain regions are approximately the same, and are greater than the perimeter of the channel region at locations immediately adjacent the channel region, and wherein the smallest perimeter of the nanowire is at the locations where the source and drain regions are immediately adjacent the channel region;
forming a pair of conductive contacts, a first of the pair of conductive contacts completely surrounding and in contact with the entire perimeter of the source region, and a second of the pair of conductive contacts completely surrounding and in contact with the entire perimeter of the drain region, wherein the pair of conductive contacts has an uppermost surface co-planar with an uppermost surface of the gate electrode stack
forming a pair of spacers disposed between the gate electrode stack and the pair of conductive contacts, wherein an intervening semiconductor material is below and in contact with the nanowire but not along sidewalls of the nanowire at a location beneath the pair of spacers.

### Claim 20 (depends on 19)

The method of claim 19, wherein forming the channel region comprises removing a portion of the nanowire.

### Claim 21 (depends on 19)

The method of claim 19, wherein forming the pair of source and drain regions comprises forming a doping layer on and completely surrounding the perimeter of each of the source and drain regions.

### Claim 22 (depends on 19)

The method of claim 19, wherein forming the pair of source and drain regions comprises growing a portion of the nanowire.

### Claim 23 (depends on 22)

The method of claim 22, wherein the nanowire consists essentially of silicon, and growing the portion of the nanowire comprises forming exposed <111> silicon surfaces along the entire perimeter of each of the source and drain regions.

### Claim 24 (depends on 23)

The method of claim 23, wherein forming the exposed <111> silicon surfaces comprises using a deposition and selective etch process.