# US 10,483,383 B2 · Semiconductor device including a gate contact structure

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- Number: US 10,483,383 B2
- Document ID: US10483383B2
- Status: Granted
- Kind: B2
- Application number: 15/921,044
- Filed: 2018-03-14
- Published: 2018-09-20
- Granted: 2019-11-19
- Earliest claimed: 2017-03-15
- Assignees: Infineon Technologies Dresden GmbH
- Applicants: Infineon Technologies Dresden GmbH & Co. KG
- Inventors: Joachim Weyers; Katarzyna Kowalik-Seidl; Andreas Schloegl; Enrique Vecino Vazquez
- Web page: https://patentgrep.com/patent/US10483383B2

## CPC

- H10D 84/125: {the built-in components being resistive elements, e.g. BJT having a built-in ballasting resistor}
- H10D 12/035: {Etching a recess in the emitter region (having a recessed gate H10D12/038)}
- H10D 12/461: {having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions}
- H10D 30/64: Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/665: {having edge termination structures}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 64/01: Manufacture or treatment
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 64/605: {Source, drain, or gate electrodes for FETs comprising highly resistive materials}
- H10D 84/121: {BJTs having built-in components}
- H10D 84/141: {VDMOS having built-in components}
- H10D 84/403: {Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors}
- H10D 84/817: {Combinations of field-effect devices and resistors only}
- H10D 1/47: Resistors having no potential barriers
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 12/491: {having both emitter contacts and collector contacts in the same substrate side}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/112: {comprising multiple field plate segments}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a semiconductor body. The semiconductor body has a first surface and a second surface opposite to the first surface. A transistor cell structure is provided in the semiconductor body. A gate contact structure includes a gate line electrically coupled to a gate electrode layer of the transistor cell structure, and a gate pad electrically coupled to the gate line. A gate resistor structure is electrically coupled between the gate pad and the gate electrode layer. An electric resistivity of the gate resistor structure is greater than the electric resistivity of the gate electrode layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor body having a first surface and a second surface opposite to the first surface;
a transistor cell structure in the semiconductor body;
a gate contact structure comprising a gate line electrically coupled to a gate electrode layer of the transistor cell structure, and a gate pad electrically coupled to the gate line to form an electrical pathway between the gate pad and the gate electrode layer; and
a gate resistor structure separate from the gate contact structure, integrated in the electrical pathway between the gate pad and the gate electrode layer, and formed on a different isolation layer than the gate contact structure,
wherein an electric resistivity of the gate resistor structure is greater than the electric resistivity of the gate electrode layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising a source contact structure overlapping the transistor cell structure, the source contact structure being electrically connected to source regions of the transistor cell structure.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the gate line at least partly surrounds the source contact structure.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the gate resistor structure is electrically coupled between the gate pad and the gate line.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the gate resistor structure is electrically coupled between the gate line and the gate electrode layer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein an edge portion of the gate resistor structure and an edge portion of the gate electrode layer are arranged along a same line parallel to the gate line.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the gate resistor structure comprises a polycrystalline silicon layer having a sheet resistance higher than 10 Ohm/square.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the source contact structure and the gate contact structure are patterned parts of a same metal wiring layer.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, further comprising a first isolation layer on the first surface of the semiconductor body, wherein the gate resistor structure and the gate electrode layer are formed on the first isolation layer.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, further comprising a second isolation layer on the gate resistor structure and the gate electrode layer, wherein the gate contact structure is formed on the second isolation layer.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the gate resistor structure comprises gate resistor elements electrically coupled in parallel between the gate line and the gate electrode layer of the transistor cell structure.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein an electrical resistance of the gate resistor elements decreases with an increasing electrical resistance of the gate line from the gate pad to the gate resistor elements, respectively.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein a first terminal of the gate resistor structure is electrically connected with the gate line by a first electric contact structure and a second terminal of the gate resistor structure is electrically connected with the gate electrode layer by a second electric contact structure.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the second electric contact structure comprises two electric contact elements, which are electrically shunted by a bridging element.

### Claim 15 (depends on 13)

The semiconductor device of claim 13, wherein at least a part of the second electric contact structure is located within a lateral recess of the gate line.

### Claim 16

A semiconductor device, comprising:
a semiconductor body having a first surface and a second surface opposite to the first surface;
a transistor cell structure in the semiconductor body;
a gate contact structure comprising a gate line electrically coupled to a gate electrode layer of the transistor cell structure, and a gate pad electrically coupled to the gate line to form an electrical pathway between the gate pad and the gate electrode layer; and
a gate interconnecting structure separate from the gate contact structure and comprising gate interconnecting elements protruding from the gate electrode layer and being electrically coupled in parallel to the gate line,
wherein the gate interconnecting structure is formed on a different isolation layer than the gate contact structure,
wherein a minimum resistance of the gate interconnecting elements is greater than 40 Ohm.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the gate interconnecting elements are formed as comb segments protruding from the gate electrode layer in a lateral plane.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, wherein an electrical resistance of the gate interconnecting elements decreases with an increasing electrical resistance of the gate line from the gate pad to the gate interconnecting elements, respectively.

### Claim 19

A method for manufacturing a semiconductor device, the method comprising:
forming a transistor cell structure in a semiconductor body having a first surface and a second surface opposite to the first surface;
forming a gate contact structure comprising a gate line electrically coupled to a gate electrode layer of the transistor cell structure, and a gate pad electrically coupled to the gate line to form an electrical pathway between the gate pad and the gate electrode layer; and
forming a gate resistor structure separate from the gate contact structure, integrated in the electrical pathway between the gate pad and the gate electrode layer, and formed on a different isolation layer than the gate contact structure,
wherein an electric resistivity of the gate resistor structure is greater than the electric resistivity of the gate electrode layer.

### Claim 20

A method for manufacturing a semiconductor device, the method comprising:
forming a transistor cell structure in a semiconductor body having a first surface and a second surface opposite to the first surface;
forming a gate contact structure comprising a gate line electrically coupled to a gate electrode layer of the transistor cell structure, and a gate pad electrically coupled to the gate line to form an electrical pathway between the gate pad and the gate electrode layer; and
forming a gate interconnecting structure separate from the gate contact structure and comprising gate interconnecting elements protruding from the gate electrode layer and electrically coupled in parallel to the gate line, the gate interconnecting structure being formed on a different isolation layer than the gate contact structure,
wherein a minimum resistance of the gate interconnecting elements is greater than 40 Ohm.