# US 10,483,381 B2 · Semiconductor device and method for fabricating semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,381 B2 - Document ID: US10483381B2 - Status: Granted - Kind: B2 - Application number: 16/024,562 - Filed: 2018-06-29 - Published: 2018-11-08 - Granted: 2019-11-19 - Earliest claimed: 2015-12-31 - Assignees: Huawei Technologies Co., Ltd. - Applicants: Huawei Technologies Co., Ltd. - Inventors: Jing Zhao; Chen-Xiong Zhang - Web page: https://patentgrep.com/patent/US10483381B2 ## CPC - H10D 48/383: {Quantum effect devices, e.g. of devices using quantum reflection, diffraction or interference effects} - H10D 1/47: Resistors having no potential barriers - H10D 1/68: Capacitors having no potential barriers - H10D 12/021: {of gated diodes, e.g. field-controlled diodes [FCD]} - H10D 12/211: {Gated diodes} - H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions} - H10D 62/142: {Anode regions of thyristors or collector regions of gated bipolar-mode devices} - H10D 64/311: {Gate electrodes for field-effect devices} - H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} - H10D 84/0151: {Manufacturing their isolation regions} - H10D 84/016: {the components including vertical IGFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10D 84/83: of only insulated-gate FETs [IGFET] - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device and a method for fabricating a semiconductor device are disclosed. The semiconductor device includes a tunnel field-effect transistor and a planar device. The tunnel field-effect transistor includes a first substrate and a first electrical element, and the first electrical element is formed on one side of the first substrate; the planar device includes a second substrate and a second electrical element, the second substrate and the first substrate are an integrated structure and form a main substrate, the second electrical element is formed on one side of the second substrate, and the second electrical element and the first electrical element are disposed on a same side of the main substrate; and the planar device includes any one of a metal oxide semiconductor transistor, a capacitor, and a resistor. ## Claims ### Claim 1 A semiconductor device, comprising: a tunnel field-effect transistor comprising: a first substrate; and a first electrical element, wherein the first electrical element is formed on one side of the first substrate, wherein the first electrical element comprises: a first drain region; a second drain region, wherein the first drain region and the second drain region are opposite to each other and separated by a part of the first substrate; a first shallow trench isolation region; a second shallow trench isolation region, wherein the first drain region and the second drain region are disposed between the first shallow trench isolation region and the second shallow trench isolation region; a planar device comprising: a second substrate; and a second electrical element, wherein the second substrate and the first substrate are an integrated structure and form a main substrate, wherein the second electrical element is formed on one side of the second substrate, wherein the second electrical element and the first electrical element are disposed on a same side of the main substrate, and wherein the planar device comprises at least one of a metal oxide semiconductor transistor, a capacitor, or a resistor. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the first substrate comprises a first surface and a second surface that are disposed opposite to each other, wherein the second substrate comprises a third surface and a fourth surface that are disposed opposite to each other, wherein the first substrate is in contact with the second substrate, wherein the third surface is flush with the first surface, and wherein the fourth surface is flush with the second surface. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein the first shallow trench isolation region and the second shallow trench isolation region are embedded into the first substrate from the first surface, wherein one end of the first shallow trench isolation region is flush with the first surface, wherein one end of the second shallow trench isolation region is flush with the first surface, and wherein the second shallow trench isolation region and the first shallow trench isolation region are opposite to each other and separated by a part of the first substrate. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein the first electrical element further comprises a first source region, a first insulation layer, a first gate dielectric layer, and a first gate region, wherein the first drain region and the second drain region are embedded into the first substrate from the first surface, wherein one end of the first drain region is flush with the first surface, wherein one end of the second drain region is flush with the first surface, wherein the first drain region is in contact with the first shallow trench isolation region, wherein the second drain region is in contact with the second shallow trench isolation region, wherein the first source region is disposed in a protruding manner on the first surface, wherein the first source region is located between the first drain region and the second drain region, wherein the first insulation layer is disposed in a protruding manner on the first surface, wherein the first insulation layer is symmetrically disposed on both sides of the first source region connected to a region between the first drain region and the first source region and a region between the second drain region and the first source region, wherein a thickness of the first insulation layer is less than a height of the first source region, wherein the first gate dielectric layer is symmetrically disposed on the both sides of the first source region and is attached to a surface of the first source region and a surface of the first insulation layer, and wherein the first gate region is disposed around the first gate dielectric layer. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein the first gate dielectric layer comprises a first gate dielectric portion and a second gate dielectric portion, wherein the first gate dielectric portion is stacked on the first insulation layer, wherein one end of the second gate dielectric portion is connected to the first gate dielectric portion, and wherein the second gate dielectric portion is attached to the surface of the first source region. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein the first gate region comprises a first part and a second part, wherein the first part is stacked on the first gate dielectric portion, wherein one end of the second part is connected to one end of the first part, and wherein the second part is attached to a surface of the second gate dielectric portion. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein the first gate dielectric layer further comprises a third gate dielectric portion, wherein the third gate dielectric portion is connected to one end of the second gate dielectric portion that is away from the first gate dielectric portion, wherein the third gate dielectric portion covers one end of the first source region that is away from the substrate, wherein the first gate region further comprises a third part connected to one end of the second part that is away from the first part, and wherein the third part covers the third gate dielectric portion. ### Claim 8 (depends on 6) The semiconductor device according to claim 6, wherein the first electrical element further comprises a first drain, a second drain, a first source, and two first gates, wherein the first drain, the second drain, the first source, and the two first gates correspondingly connect to the first drain region, the second drain region, the first source region, and the second part of the first gate region, respectively, and wherein the two first gates are respectively disposed on both sides of the first source. ### Claim 9 (depends on 7) The semiconductor device according to claim 7, wherein the first electrical element further comprises a first drain, a second drain, a first source, and three first gates, wherein the first drain, the second drain, the first source, and the three first gates correspondingly connect to the first drain region, the second drain region, the first source region, and the first gate region during disposing, wherein two of the first gates are connected to the second part and respectively disposed on both sides of the first source, and wherein another first gate excluding the two of the first gates is connected to the third part. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein the second electrical element comprises a third shallow trench isolation region and a fourth shallow trench isolation region, wherein the third shallow trench isolation region and the fourth shallow trench isolation region are embedded into the second substrate from the third surface, wherein one end of the third shallow trench isolation region is flush with the third surface, wherein one end of the fourth shallow trench isolation region is flush with the third surface, and wherein the fourth shallow trench isolation region and the third shallow trench isolation region are disposed opposite to each other and separated by a part of the second substrate. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein the planar device is the metal oxide semiconductor transistor, wherein the second electrical element comprises a second source region, a third drain region, a second gate dielectric layer, and a second gate region, wherein the second source region and the third drain region are embedded into the second substrate from the third surface, wherein one end of the second source region is flush with the third surface, wherein one end of the third drain region is flush with the third surface, wherein the second source region and the third drain region are opposite to each other separated by a part of the second substrate and disposed between the third shallow trench isolation region and the fourth shallow trench isolation region, wherein the second source region is in contact with the third shallow trench isolation region, wherein the third drain region is in contact with the fourth shallow trench isolation region, wherein the second gate dielectric layer is disposed in a protruding manner on the third surface, wherein the second gate dielectric layer is disposed between the second source region and the third drain region, wherein the second gate region is stacked on the second gate dielectric layer, and wherein the second gate region is in contact with the second gate dielectric layer. ### Claim 12 (depends on 11) The semiconductor device according to claim 11, wherein the second electrical element further comprises a second source, a third drain, and a second gate, and wherein the second source, the third drain, and the second gate are correspondingly connected to the second source region, the third drain region, and the second gate region, respectively. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein the second electrical element further comprises a second isolation layer, wherein the second isolation layer is located at a same layer as the first isolation layer, wherein the second isolation layer covers the second source region, the third drain region, and the second gate region, wherein a seventh through hole, an eighth through hole, and a ninth through hole are disposed at the second isolation layer, wherein the seventh through hole is disposed corresponding to the second source region, wherein the second source is connected to the second source region using the seventh through hole, wherein the eighth through hole is disposed corresponding to the third drain region, wherein the third drain is connected to the third drain region using the eighth through hole, wherein the ninth through hole is disposed corresponding to the second gate region, and wherein the second gate is connected to the second gate region using the ninth through hole. ### Claim 14 (depends on 11) The semiconductor device according to claim 11, wherein the first drain region, the second drain region, the second source region, and the third drain region are first-type ion heavily-doped regions, wherein the first source region is a second-type ion heavily-doped region, wherein the first-type ion heavily-doped region is an N-type ion heavily-doped region and the second-type ion heavily-doped region is a P-type ion heavily-doped region, or wherein the first-type ion heavily-doped region is a P-type ion heavily-doped region and the second-type ion heavily-doped region is an N-type ion heavily-doped region. ### Claim 15 (depends on 10) The semiconductor device according to claim 10, wherein the planar device is the capacitor, wherein the second electrical element comprises a first doping region, a second insulation layer, a third gate dielectric layer, and a third gate region, wherein the first doping region is embedded into the second substrate from the third surface; one end of the first doping region is flush with the third surface, wherein the first doping region is disposed between the third shallow trench isolation region and the fourth shallow trench isolation region, wherein one end of the first doping region is in contact with the third shallow trench isolation region, wherein another end of the first doping region is in contact with the fourth shallow trench isolation region wherein the second insulation layer is disposed in the middle of the first doping region, wherein the second insulation layer does not cover the both ends of the first doping region, wherein the third gate dielectric layer is stacked on the second insulation layer, and wherein the third gate region is stacked on the third gate dielectric layer. ### Claim 16 (depends on 15) The semiconductor device according to claim 15, wherein the second electrical element further comprises a first electrode, a second electrode, and a third electrode, wherein the first electrode and the second electrode correspondingly connect to the both ends of the first doping region, respectively, and wherein the third electrode is connected to the third gate region. ### Claim 17 (depends on 10) The semiconductor device according to claim 10, wherein the planar device is the resistor, wherein the second electrical element comprises a second doping region, wherein the second doping region is embedded into the second substrate from the third surface, wherein one end of the second doping region is flush with the third surface, wherein the second doping region is disposed between the third shallow trench isolation region and the fourth shallow trench isolation region, wherein one end of the second doping region is in contact with the third shallow trench isolation region, and wherein another end of the second doping region is in contact with the fourth shallow trench isolation region. ### Claim 18 (depends on 17) The semiconductor device according to claim 17, wherein the second electrical element further comprises a fourth electrode and a fifth electrode, and the fourth electrode and the fifth electrode are correspondingly connected to the both ends of the second doping region, respectively. ### Claim 19 A method for fabricating a semiconductor device, comprising: providing a main substrate comprising a first substrate and a second substrate that are adjacent to each other, wherein the first substrate comprises a first surface and a second surface that are disposed opposite to each other, wherein the second substrate comprises a third surface and a fourth surface that are disposed opposite to each other, wherein the third surface is flush with the first surface, and wherein the fourth surface is flush with the second surface; forming a first electrical element on one side of the first substrate by forming a first shallow trench isolation region and a second shallow trench isolation region; and forming a first drain region and a second drain region, wherein the first drain region and the second drain region are opposite to each other and separated by a part of the first substrate, and wherein the first drain region and the second drain region are disposed between the first shallow trench isolation region and the second shallow trench isolation region; and forming a second electrical element on one side of the second substrate, wherein the second electrical element and the first electrical element are disposed on a same side of the main substrate, wherein the first substrate and the first electrical element constitute a tunnel field-effect transistor, wherein the second substrate and the second electrical element constitute a planar device, and wherein the planar device comprises at least one of a metal oxide semiconductor transistor, a capacitor, or a resistor. ### Claim 20 (depends on 19) The method according to claim 19, further comprising forming, from the third surface, a third shallow trench isolation region and a fourth shallow trench isolation region that are embedded into the second substrate, wherein one end of the first shallow trench isolation region is flush with the first surface, wherein one end of the second shallow trench isolation region is flush with the first surface, wherein the second shallow trench isolation region and the first shallow trench isolation region are disposed opposite to each other and separated by a part of the first substrate, wherein one end of the third shallow trench isolation region is flush with the third surface, wherein one end of the fourth shallow trench isolation region is flush with the third surface, and wherein the fourth shallow trench isolation region and the third shallow trench isolation region are disposed opposite to each other and separated by a part of the second substrate.