# US 10,483,380 B2 · Semiconductor device and method of manufacturing the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,483,380 B2
- Document ID: US10483380B2
- Status: Granted
- Kind: B2
- Application number: 15/655,974
- Filed: 2017-07-21
- Published: 2018-10-25
- Granted: 2019-11-19
- Earliest claimed: 2017-04-20
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Aryan Afzalian
- Web page: https://patentgrep.com/patent/US10483380B2

## CPC

- H10D 48/383: {Quantum effect devices, e.g. of devices using quantum reflection, diffraction or interference effects}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 12/211: {Gated diodes}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 62/141: {Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs}
- H10D 62/142: {Anode regions of thyristors or collector regions of gated bipolar-mode devices}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/82: Heterojunctions
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6728: {Vertical TFTs}
- H10D 62/123: {comprising junctions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device includes a source region having a first dopant and a drain region having a second dopant. The first dopant is different from the second dopant. A channel region is in between the source and drain region. The channel region is intrinsic. A tunnel barrier layer disposed in between the drain region and the channel region. A gate stack disposed on the channel region. The source region comprises GaSb, the drain region comprises InAs, the channel region comprises InAs, and the tunnel barrier layer comprises InGaAs. The gate stack wraps around the channel region and partially overlaps the tunnel barrier layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a source region having a first dopant;
a drain region having a second dopant, the first dopant being different from the second dopant;
a channel region between the source region and drain region, wherein the channel region is intrinsic;
a tunnel barrier layer between the drain region and the channel region, wherein a material of the tunnel barrier layer having a larger bandgap than the channel region; and
a gate stack disposed on the channel region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the gate stack overlaps the tunnel barrier layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the gate stack overlaps a portion of the tunnel barrier layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the gate stack does not overlap the tunnel barrier layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the source region comprises GaSb, the drain region comprises InAs, and the tunnel barrier layer comprises InGaAs.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the gate stack wraps portions of the channel region and the tunnel barrier layer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the channel region has the same material as the drain region.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising a semiconductor column, wherein a first portion of the semiconductor column is the source region, a second portion of the semiconductor column is the channel region, and a third portion of the semiconductor column is the drain region.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the tunnel barrier layer is stacked on a portion of the channel region, the drain region is disposed on the tunnel barrier layer, and the source region and the drain region are offset.

### Claim 10

A method of fabricating a semiconductor device, the method comprising:
forming a channel region on a semiconductor substrate, wherein the channel region is intrinsic;
forming a tunnel barrier layer next to the channel region;
forming source and drain regions on the semiconductor substrate, wherein the tunnel barrier layer is between the channel region and drain region and is spaced from the source region, a material of the tunnel barrier layer has a larger bandgap than the channel region; and
forming a gate stack on the channel region.

### Claim 11 (depends on 10)

The method of claim 10, wherein the forming the source and drain regions on the semiconductor substrate comprising:
introducing a first dopant to the source region; and
introducing a second dopant to the drain region.

### Claim 12 (depends on 10)

The method of claim 10, wherein forming the tunnel barrier layer comprises:
etching a portion of the drain region to form an opening defined by thedrain region; and
forming the tunnel barrier layer in the opening.

### Claim 13 (depends on 10)

The method of claim 10, wherein forming the tunnel barrier layer comprises:
etching a portion of the semiconductor substrate between the channel region and the drain region to form an opening in the semiconductor substrate; and
forming the tunnel barrier layer in the opening.

### Claim 14 (depends on 10)

The method of claim 10, wherein forming the tunnel barrier layer is performed such that a material of the tunnel barrier layer has a larger bandgap than the drain region.

### Claim 15 (depends on 10)

The method of claim 10, wherein forming the tunnel barrier layer comprises:
forming a nanowire layer and a tunnel barrier above the nanowire layer; and
etching the nanowire layer and the tunnel barrier to form the tunnel barrier layer above the channel region.

### Claim 16 (depends on 10)

The method of claim 10, wherein forming the tunnel barrier layer comprises:
forming a gate spacer on a sidewall of the gate stack;
etching the spacer to expose a top surface of the channel region; and
forming the tunnel barrier layer above the top surface of the channel region.

### Claim 17

A semiconductor device, comprising:
a source region having a first dopant;
a drain region having a second dopant, the first dopant being different from the second dopant;
a channel region between the source region and drain region, wherein the channel region is intrinsic;
a tunnel barrier layer between the drain region and the channel region, wherein a material of the tunnel barrier layer having a larger bandgap than the channel region; and
a gate stack disposed on the channel region;
wherein the drain region is disposed over the tunnel barrier layer which is disposed over the channel region, and the channel region is disposed on the source region.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the gate stack includes a high-k dielectric layer, a metal layer, and an interlayer dielectric layer, and the metal layer is interposed between the high-k dielectric layer and the interlayer dielectric layer.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein the gate stack wraps the channel region and the tunnel barrier layer.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, further comprising a spacer over the gate stack, wherein the spacer surrounds a sidewall of the drain region.