# US 10,483,379 B2 · High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss

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- Number: US 10,483,379 B2
- Document ID: US10483379B2
- Status: Granted
- Kind: B2
- Application number: 15/867,860
- Filed: 2018-01-11
- Published: 2018-05-17
- Granted: 2019-11-19
- Earliest claimed: 2014-09-04
- Assignees: GlobalWafers Co., Ltd.
- Applicants: SunEdison Semiconductor Limited (UEN201334164H)
- Inventors: Qingmin Liu; Gang Wang
- Web page: https://patentgrep.com/patent/US10483379B2

## CPC

- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/2924: {Structures}
- H10P 14/3416: {Nitrides}
- H10P 14/3458: {Monocrystalline}
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 90/00: Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P 90/1916: {with separation or delamination along an ion implanted layer, e.g. Smart-cut}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10W 10/041: {of isolation regions comprising polycrystalline semiconductor materials}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 10/40: Isolation regions comprising polycrystalline semiconductor materials
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a semiconductor nitride layer in contact with the semiconductor handle substrate, the semiconductor nitride layer selected from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof; a dielectric layer in contact with the semiconductor nitride layer; and a semiconductor device layer in contact with the dielectric layer.

## Claims

### Claim 1

A method of forming a multilayer structure, the method comprising:
forming a crystalline semiconductor nitride layer on a front surface of a silicon wafer handle substrate, wherein the crystalline semiconductor nitride layer is selected from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof and further wherein the crystalline semiconductor nitride layer is formed by metalorganic chemical vapor deposition occurring by a reaction between an organic compound or a metalorganic compound and a nitrogen-containing precursor and wherein the silicon wafer handle substrate comprises two major, generally parallel surfaces, one of which is the front surface of the silicon wafer handle substrate and the other of which is a back surface of the silicon wafer handle substrate, a circumferential edge joining the front and back surfaces of the silicon wafer handle substrate, and a bulk region between the front and back surfaces of the silicon wafer handle substrate, wherein the silicon wafer handle substrate has a minimum bulk region resistivity of at least about 500 ohm-cm;
forming a silicon dioxide layer having a thickness between about 500 nanometers and about 2 micrometers in interfacial contact with the crystalline semiconductor nitride layer; and
bonding a dielectric layer in interfacial contact with a front surface of a semiconductor donor substrate to the silicon dioxide layer in interfacial contact with the crystalline semiconductor nitride layer to thereby form a bonded structure, wherein the semiconductor donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the semiconductor donor substrate and the other of which is a back surface of the semiconductor donor substrate, a circumferential edge joining the front and back surfaces of the semiconductor donor substrate, and a central plane between the front and back surfaces of the semiconductor donor substrate.

### Claim 2 (depends on 1)

The method of claim 1 wherein the silicon wafer handle substrate is sliced from a single crystal silicon ingot grown by the Czochralski method or the float zone method.

### Claim 3 (depends on 1)

The method of claim 1 wherein the silicon wafer handle substrate has a bulk resistivity between about 500 Ohm-cm and about 100,000 Ohm-cm.

### Claim 4 (depends on 1)

The method of claim 1 wherein the silicon wafer handle substrate has a bulk resistivity between about 1000 Ohm-cm and about 100,000 Ohm-cm.

### Claim 5 (depends on 1)

The method of claim 1 wherein the silicon wafer handle substrate has a bulk resistivity between about 1000 Ohm-cm and about 10,000 Ohm-cm.

### Claim 6 (depends on 1)

The method of claim 1 wherein the silicon wafer handle substrate has a bulk resistivity between about 2000 Ohm-cm and about 10,000 Ohm-cm.

### Claim 7 (depends on 1)

The method of claim 1 wherein the silicon wafer handle substrate has a bulk resistivity between about 3000 Ohm-cm and about 10,000 Ohm-cm.

### Claim 8 (depends on 1)

The method of claim 1 wherein the silicon wafer handle substrate has a bulk resistivity between about 3000 Ohm-cm and about 5,000 Ohm-cm.

### Claim 9

A method of forming a multilayer structure, the method comprising:
forming an amorphous semiconductor nitride layer on a front surface of a silicon wafer handle substrate, wherein the amorphous semiconductor nitride is selected from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof and further wherein the amorphous semiconductor nitride layer is formed by metalorganic chemical vapor deposition occurring by a reaction between an organic compound or a metalorganic compound and a nitrogen-containing precursor and wherein the silicon wafer handle substrate comprises two major, generally parallel surfaces, one of which is the front surface of the silicon wafer handle substrate and the other of which is a back surface of the silicon wafer handle substrate, a circumferential edge joining the front and back surfaces of the silicon wafer handle substrate, and a bulk region between the front and back surfaces of the silicon wafer handle substrate, wherein the silicon wafer handle substrate has a minimum bulk region resistivity of at least about 500 ohm-cm:
forming a silicon dioxide layer having a thickness between about 500 nanometers and about 2 micrometers in interfacial contact with the amorphous semiconductor nitride layer; and
bonding a dielectric layer in interfacial contact with a front surface of a semiconductor donor substrate to the silicon dioxide layer in interfacial contact with the crystalline semiconductor nitride layer to thereby form a bonded structure, wherein the semiconductor donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the semiconductor donor substrate and the other of which is a back surface of the semiconductor donor substrate, a circumferential edge joining the front and back surfaces of the semiconductor donor substrate, and a central plane between the front and back surfaces of the semiconductor donor substrate.

### Claim 10 (depends on 1)

The method of claim 1 wherein the crystalline semiconductor nitride layer comprises aluminum nitride.

### Claim 11 (depends on 1)

The method of claim 1 wherein the crystalline semiconductor nitride layer comprises boron nitride.

### Claim 12 (depends on 1)

The method of claim 1 wherein the crystalline semiconductor nitride layer comprises indium nitride.

### Claim 13 (depends on 1)

The method of claim 1 wherein the crystalline semiconductor nitride layer comprises gallium nitride.

### Claim 14 (depends on 1)

The method of claim 1 wherein the crystalline semiconductor nitride layer has an average thickness of between about 1 nanometer and about 2000 nanometers.

### Claim 15 (depends on 1)

The method of claim 1 wherein the crystalline semiconductor nitride layer has an average thickness of between about 5 nanometers and about 1000 nanometers.

### Claim 16 (depends on 1)

The method of claim 1 wherein the crystalline semiconductor nitride layer has an average thickness of between about 5 nanometers and about 500 nanometers.

### Claim 17 (depends on 1)

The method of claim 1 wherein the crystalline semiconductor nitride layer has an average thickness of between about 5 nanometers and about 200 nanometers.

### Claim 18 (depends on 1)

The method of claim 1 wherein the semiconductor donor substrate comprises a silicon wafer sliced from a single crystal silicon ingot grown by the Czochralski method or the float zone method.

### Claim 19 (depends on 1)

The method of claim 1 wherein the semiconductor donor substrate comprises a silicon wafer sliced from a single crystal silicon ingot grown by the Czochralski method.

### Claim 20 (depends on 1)

The method of claim 1 wherein the dielectric layer in interfacial contact with the semiconductor donor substrate is selected from the group consisting of silicon dioxide, silicon nitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and any combination thereof.

### Claim 21 (depends on 1)

The method of claim 1 further comprising heating the bonded structure at a temperature and for a duration sufficient to strengthen the bond between the dielectric layer in interfacial contact with the semiconductor donor structure and silicon dioxide layer in interfacial contact with the crystalline semiconductor nitride layer.

### Claim 22 (depends on 1)

The method of claim 1 wherein the semiconductor donor substrate comprises an ion implanted damage layer.

### Claim 23 (depends on 22)

The method of claim 22 further comprising mechanically cleaving the bonded structure at the ion implanted damage layer of the semiconductor donor substrate to thereby prepare a cleaved structure comprising the silicon wafer handle substrate, the crystalline semiconductor nitride layer in contact with the front surface of the silicon wafer handle substrate, the silicon dioxide layer in interfacial contact with the crystalline semiconductor nitride layer, the dielectric layer in contact with the silicon dioxide layer, and a semiconductor device layer in contact with the dielectric layer.

### Claim 24 (depends on 23)

The method of claim 23 further comprising heating the cleaved structure at a temperature and for a duration sufficient to strengthen the bond between the dielectric layer and the silicon dioxide layer.