# US 10,483,375 B1 · Fin cut etch process for vertical transistor devices

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,483,375 B1
- Document ID: US10483375B1
- Status: Granted
- Kind: B1
- Application number: 16/037,305
- Filed: 2018-07-17
- Granted: 2019-11-19
- Earliest claimed: 2018-07-17
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Wenyu Xu; Chen Zhang; Kangguo Cheng; Xin Miao
- Web page: https://patentgrep.com/patent/US10483375B1

## CPC

- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 50/642: {Chemical etching}
- H10D 62/405: {Orientations of crystalline planes}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 95/062: {involving a dielectric removal step}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for fabricating a semiconductor device including a vertical transistor includes forming a fin structure from a substrate. The fin structure includes a fin. The method further includes forming a bottom source/drain region on the substrate adjacent to the fin, etching a longitudinal end portion of the fin to create a gap exposing the substrate, forming a gate and a top source/drain region, and forming a contact wrapping around a horizontal portion and a vertical portion of the bottom source/drain region in a region including a location where the longitudinal end portion of the fin was removed by the etching.

## Claims

### Claim 1

A method for fabricating a semiconductor device including a vertical transistor, comprising:
forming a fin structure from a substrate, the fin structure including a fin;
forming a bottom source/drain region on the substrate adjacent to the fin;
etching a longitudinal end portion of the fin to create a gap exposing the substrate;
forming a gate and a top source/drain region; and
forming a contact wrapping around a horizontal portion and a vertical portion of the bottom source/drain region in a region including a location where the longitudinal end portion of the fin was removed by the etching.

### Claim 2 (depends on 1)

The method of claim 1, wherein the fin structure further includes a cap layer disposed on the fin to protect the sidewalls of the fin during the formation of the bottom source/drain region.

### Claim 3 (depends on 1)

The method of claim 1, further comprising forming a bottom spacer on the bottom source/drain region, wherein the gate stack is formed on the bottom spacer.

### Claim 4 (depends on 3)

The method of claim 3, further comprising forming a top spacer on the gate stack, wherein the top source/drain region is formed on the top spacer and the fin.

### Claim 5 (depends on 1)

The method of claim 1, further comprising etching material in the region including the location where the longitudinal end portion of the fin was removed by the etching to form a trench, and filling the trench with conductive material to form the contact.

### Claim 6 (depends on 5)

The method of claim 5, wherein etching the material in the region including the location where the longitudinal end portion of the fin was removed by the etching to form the trench includes a first etching to expose the bottom spacer, and a second etching to break through the bottom spacer and recess dielectric material corresponding to the trench to expose a side wall of the bottom source/drain region within the trench.

### Claim 7 (depends on 6)

The method of claim 6, wherein the second etching uses a timed etch process.

### Claim 8 (depends on 1)

The method of claim 1, wherein the contact includes trench silicide.

### Claim 9 (depends on 1)

The method of claim 1, wherein the contact has a three-dimensional wrap-around shape.

### Claim 10

A method for fabricating a semiconductor device including a vertical transistor, comprising:
forming a fin structure from a substrate, the fin structure including a fin and a cap layer disposed on the fin;
forming a bottom source/drain region on the substrate adjacent to the fin, wherein the cap layer protects sidewalls of the fin during the formation of the bottom source/drain region;
forming a first dielectric fill on the substrate after defining an active diffusion cut region;
etching a longitudinal end portion of the fin to create a gap exposing the substrate;
filling the gap with a second dielectric fill;
forming a gate and a top source/drain region; and
forming a contact wrapping around a horizontal portion and a vertical portion of the bottom source/drain region in a region including a location where the longitudinal end portion of the fin was removed by the etching.

### Claim 11 (depends on 10)

The method of claim 10, further comprising forming a bottom spacer on the bottom source/drain region, wherein the gate stack is formed on the bottom spacer.

### Claim 12 (depends on 11)

The method of claim 11, further comprising forming a top spacer on the gate stack, wherein the top source/drain region is formed on the top spacer and the fin.

### Claim 13 (depends on 10)

The method of claim 10, further comprising etching material in the region including the location where the longitudinal end portion of the fin was removed by the etching to form a trench, and filling the trench with conductive material to form the contact.

### Claim 14 (depends on 13)

The method of claim 13, wherein etching the material in the region including the location where the longitudinal end portion of the fin was removed by the etching to form the trench includes a first etching to expose the bottom spacer, and a second etching to break through the bottom spacer and recess dielectric material corresponding to the trench to expose a side wall of the bottom source/drain region within the trench.

### Claim 15 (depends on 14)

The method of claim 14, wherein the second etching uses a timed etch process.

### Claim 16 (depends on 10)

The method of claim 10, wherein the contact includes trench silicide.

### Claim 17 (depends on 10)

The method of claim 10, wherein the at least one contact has a three-dimensional wrap-around shape.

### Claim 18

A semiconductor device including a vertical transistor, comprising:
a substrate;
a fin disposed on the substrate;
a bottom source/drain region disposed on the substrate adjacent to the fin;
a bottom spacer disposed on the bottom source/drain region;
a gate stack adjacent to the fin disposed on the bottom spacer;
a top spacer disposed on the gate stack;
a top source/drain region disposed on the top spacer and the fin; and
a contact wrapping around a horizontal portion and a vertical portion of the bottom source/drain region.

### Claim 19 (depends on 18)

The device of claim 18, wherein contact includes trench silicide.

### Claim 20 (depends on 18)

The device of claim 18, wherein the contact has a three-dimensional wrap-around shape.