# US 10,483,374 B2 · Electronic device including transistor and method for fabricating the same

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- Number: US 10,483,374 B2
- Document ID: US10483374B2
- Status: Granted
- Kind: B2
- Application number: 16/220,423
- Filed: 2018-12-14
- Published: 2019-04-25
- Granted: 2019-11-19
- Earliest claimed: 2016-02-16
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Sang-Soo Kim
- Web page: https://patentgrep.com/patent/US10483374B2

## CPC

- H10D 64/027: {by etching at gate locations}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 50/242: {of Group IV materials}
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for fabricating an electronic device is provided to include: forming a hard mask pattern over a substrate to expose a gate formation region; forming a gate trench by etching the substrate using the hard mask pattern; forming a gate insulating layer over an inner wall of the gate trench; forming a gate electrode filling a lower portion of the gate trench in which the gate insulating layer is formed; forming an insulating material covering a resultant structure in which the gate electrode is formed; forming a gate protective layer having a top surface lower than a bottom surface of the hard mask pattern; removing the hard mask pattern; recessing the substrate so that a top surface of the substrate is lower than the top surface of the gate protective layer; and forming a conductive pattern filling a space formed by the recessing of the substrate.

## Claims

### Claim 1

An electronic device comprising a transistor, wherein the transistor comprises:
a semiconductor substrate including an active region defined by an isolation layer;
a gate electrode crossing the active region; and
a landing plug contact formed over the active region at both sides of the gate electrode, and
wherein a top surface of the active region at both sides of the gate electrode has a shape that a center relatively far from the gate electrode is higher than an edge relatively near to the gate electrode.

### Claim 2 (depends on 1)

The electronic device of claim 1, wherein the transistor further comprises:
a metal silicide layer located at an interface between the landing plug contact and the active region.

### Claim 3 (depends on 1)

The electronic device of claim 1, wherein the transistor further comprises:
a memory element formed over the active region at one side of the gate electrode and coupled to the landing plug contact.

### Claim 4 (depends on 3)

The electronic device of claim 3, wherein the memory element includes a variable resistance element which is switched between different resistant states according to an applied voltage or current.

### Claim 5 (depends on 4)

The electronic device of claim 4, wherein the variable resistance element includes a pinned layer having a pinned magnetization direction, a free layer having a variable magnetization direction, and a tunnel barrier layer interposed therebetween.

### Claim 6 (depends on 1)

The electronic device of claim 1, wherein the top surface of the active region at both sides of the gate electrode has a shape that the center protrudes than the edge.

### Claim 7 (depends on 1)

The electronic device of claim 1, wherein the top surface of the active region at both sides of the gate electrode includes a convex surface.

### Claim 8 (depends on 1)

The electronic device according to claim 1, further comprising a microprocessor which includes:
a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor;
an operation unit configured to perform an operation based on a result that the control unit decodes the command; and
a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed,
wherein the transistor is part of at least one of the control unit, the operation unit and the memory unit in the microprocessor.

### Claim 9 (depends on 1)

The electronic device according to claim 1, further comprising a processor which includes:
a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data;
a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and
a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit,
wherein the transistor is part of at least one of the core unit, the cache memory unit and the bus interface in the processor.

### Claim 10 (depends on 1)

The electronic device according to claim 1, further comprising a processing system which includes:
a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command;
an auxiliary memory device configured to store a program for decoding the command and the information;
a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and
an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside,
wherein the transistor is part of at least one of the processor, the auxiliary memory device, the main memory device and the interface device in the processing system.

### Claim 11 (depends on 1)

The electronic device according to claim 1, further comprising a data storage system which includes:
a storage device configured to store data and conserve stored data regardless of power supply;
a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside;
a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and
an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside,
wherein the transistor is part of at least one of the controller, the storage device, the temporary storage device and the interface in the data storage system.

### Claim 12 (depends on 1)

The electronic device according to claim 1, further comprising a memory system which includes:
a memory configured to store data and conserve stored data regardless of power supply;
a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside;
a buffer memory configured to buffer data exchanged between the memory and the outside; and
an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside,
wherein the transistor is part of at least one of the memory controller, the memory, the buffer memory and the interface in the memory system.