# US 10,483,373 B2 · Semiconductor device

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- Number: US 10,483,373 B2
- Document ID: US10483373B2
- Status: Granted
- Kind: B2
- Application number: 16/039,371
- Filed: 2018-07-19
- Published: 2019-02-14
- Granted: 2019-11-19
- Earliest claimed: 2017-08-11
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sun-Ki Min
- Web page: https://patentgrep.com/patent/US10483373B2

## CPC

- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/511: {for IGFETs}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8316: {the IGFETs characterised by having gate sidewall spacers specially adapted for integration}
- H10D 84/834: {comprising FinFETs}
- H10P 76/408: {characterised by their sizes, orientations, dispositions, behaviours or shapes}
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device including a first insulating interlayer on a substrate; a second insulating interlayer on the first insulating interlayer; a gate structure extending through the first insulating interlayer and the second insulating interlayer on the substrate, a lower portion of the gate structure having a first width, and an upper portion of the gate structure having a second width that is greater than the first width and that gradually increases from a bottom toward a top thereof; and a spacer structure on a sidewall of the gate structure, a width of an upper portion of the spacer structure being less than a width of a lower portion of the spacer structure.

## Claims

### Claim 1

A semiconductor device, comprising:
a first insulating interlayer on a substrate;
a second insulating interlayer on the first insulating interlayer;
a gate structure extending through the first insulating interlayer and the second insulating interlayer on the substrate, a lower portion of the gate structure having a constant first width, and an upper portion of the gate structure having a second width that is greater than the first width and that gradually increases from a bottom toward a top thereof; and
a spacer structure on a sidewall of the gate structure, a width of an upper portion of the spacer structure being less than a width of a lower portion of the spacer structure.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the width of the upper portion of the spacer structure gradually decreases from a bottom toward a top thereof.

### Claim 3 (depends on 1)

The semiconductor device as claimed in claim 1, wherein:
each of opposite sidewalls of the spacer structure has a slope with respect to an upper surface of the substrate, and
directions of the slopes of the opposite sidewalls of the spacer structure are different from each other.

### Claim 4 (depends on 1)

The semiconductor device as claimed in claim 1, wherein a distance from an upper sidewall of the spacer structure to a central portion of the spacer structure decreases from a bottom toward a top thereof.

### Claim 5 (depends on 1)

The semiconductor device as claimed in claim 1, wherein:
the spacer structure includes a plurality of spacers that are sequentially stacked, and
at least one of the plurality of spacers includes a low dielectric material having a dielectric constant lower than a dielectric constant of silicon nitride.

### Claim 6 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the upper portion of the spacer structure and the lower portion of the spacer structure have oxygen concentrations that are different from each other.

### Claim 7 (depends on 6)

The semiconductor device as claimed in claim 6, wherein the oxygen concentration of the upper portion of the spacer structure is greater than the oxygen concentration of the lower portion of the spacer structure.

### Claim 8 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the upper portion of the gate structure has a slope with respect to an upper surface of the substrate.

### Claim 9 (depends on 1)

The semiconductor device as claimed in claim 1, wherein:
the gate structure is in an opening extending through the first insulating interlayer and the second insulating interlayer, and
the gate structure includes a plurality of gate electrode layers that are sequentially stacked.

### Claim 10 (depends on 9)

The semiconductor device as claimed in claim 9, wherein:
the gate structure includes a lower gate structure, an upper gate structure, and a hard mask, and
the lower gate structure includes a gate insulation layer on an inner wall of the opening and the plurality of gate electrode layers that are sequentially stacked on the gate insulation layer.

### Claim 11 (depends on 10)

The semiconductor device as claimed in claim 10, wherein the upper gate structure:
covers the lower gate structure, and
includes a metal.

### Claim 12

A semiconductor device, comprising:
a first insulating interlayer on a substrate, the substrate including first and second regions;
a second insulating interlayer on the first insulating interlayer;
first gate structures extending through the first insulating interlayer and the second insulating interlayer on the first region of the substrate, a lower portion of each of the first gate structures having a first width, and an upper portion of each of the first gate structures having a second width that is greater than the first width and that gradually increases from a bottom toward a top thereof;
a first spacer structure on a sidewall of each of the first gate structures;
second gate structures extending through the first insulating interlayer and the second insulating interlayer on the second region of the substrate, a lower portion of each of the second gate structures having a third width, and an upper portion of each of the second gate structures having a fourth width that is greater than the third width and that gradually increases from a bottom toward a top thereof; and
a second spacer structure on a sidewall of each of the second gate structures, an upper end of the second spacer structure having a height that is different from a height of an upper end of the first spacer structure,
wherein a first distance between the first gate structures is less than a second distance between the second gate structures.

### Claim 13 (depends on 12)

The semiconductor device as claimed in claim 12, wherein:
an upper surface of a portion of the first insulating interlayer on the first region of the substrate is higher than an upper surface of a portion of the first insulating interlayer on the second region of the substrate, and
wherein an upper surface of a portion of the second insulating interlayer on the first region of the substrate is coplanar with an upper surface of a portion of the second insulating interlayer on the second region of the substrate.

### Claim 14 (depends on 12)

The semiconductor device as claimed in claim 12, wherein the height of the upper end of the first spacer structure is higher than the height of the upper end of the second spacer structure.

### Claim 15 (depends on 12)

The semiconductor device as claimed in claim 12, wherein:
a width of an upper portion of the first spacer structure is less than a width of a lower portion of the first spacer structure, and
a width of an upper portion of the second spacer structure is less than a width of a lower portion of the second spacer structure.

### Claim 16 (depends on 12)

The semiconductor device as claimed in claim 12, wherein a height of the upper portion of each of the first gate structures is greater than a height of the upper portion of each of the second gate structures.

### Claim 17 (depends on 12)

The semiconductor device as claimed in claim 12, wherein:
an upper portion of the first spacer structure has an oxygen concentration that is greater than an oxygen concentration of a lower portion of the first spacer structure, and
an upper portion of the second spacer structure has an oxygen concentration that is greater than an oxygen concentration of a lower portion of the second spacer structure.

### Claim 18

A semiconductor device, comprising:
a first insulating interlayer on a substrate;
a second insulating interlayer on the first insulating interlayer;
a gate structure extending through the first insulating interlayer and the second insulating interlayer on the substrate, a lower portion of the gate structure having a first width, and an upper portion of the gate structure having a second width that is greater than the first width and that gradually increases from a bottom toward a top thereof; and
a spacer structure on a sidewall of the gate structure,
wherein an upper portion of the spacer structure has an oxygen concentration that is different from an oxygen concentration of a lower portion of the spacer structure.

### Claim 19 (depends on 18)

The semiconductor device as claimed in claim 18, wherein a width of the upper portion of the spacer structure is less than a width of the lower portion of the spacer structure.

### Claim 20 (depends on 18)

The semiconductor device as claimed in claim 18, wherein a sidewall of the upper portion of the gate structure has a slope with respect to an upper surface of the substrate.