# US 10,483,372 B2 · Spacer structure with high plasma resistance for semiconductor devices

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- Number: US 10,483,372 B2
- Document ID: US10483372B2
- Status: Granted
- Kind: B2
- Application number: 15/874,278
- Filed: 2018-01-18
- Published: 2019-04-04
- Granted: 2019-11-19
- Earliest claimed: 2017-09-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Wan-Yi Kao; Chung-Chi Ko
- Web page: https://patentgrep.com/patent/US10483372B2

## CPC

- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0293: {using formation of insulating sidewall spacers}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/01328: {by defining the conductor using a sidewall spacer mask, a transformation under a mask or a plating at a sidewall}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 84/83125: {the IGFETs characterised by having shared source or drain regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Semiconductor device structures comprising a spacer feature having multiple spacer layers are provided. In one example, a semiconductor device includes an active area on a substrate, the active area comprising a source/drain region, a gate structure over the active area, the source/drain region being proximate the gate structure, a spacer feature having a first portion along a sidewall of the gate structure and having a second portion along the source/drain region, wherein the first portion of the spacer feature comprises a bulk spacer layer along the sidewall of the gate structure, wherein the second portion of the spacer feature comprises the bulk spacer layer and a treated seal spacer layer, the treated seal spacer layer being disposed along the source/drain region and between the bulk spacer layer and the source/drain region, and a contact etching stop layer on the spacer feature.

## Claims

### Claim 1

A semiconductor device, comprising:
an active area on a substrate, the active area comprising a source/drain region;
a gate structure over the active area, the source/drain region being proximate the gate structure, wherein the gate structure comprises a metal gate electrode disposed on a high dielectric constant layer;
a spacer feature having a first portion along a sidewall of the gate structure and having a second portion along the source/drain region, wherein the first portion of the spacer feature comprises a bulk spacer layer along the sidewall of the gate structure, wherein the second portion of the spacer feature comprises the bulk spacer layer and a treated seal spacer layer, the treated seal spacer layer being disposed along the source/drain region and between the bulk spacer layer and the source/drain region; and
a contact etching stop layer on the spacer feature.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
an interlayer dielectric layer on the contact etching stop layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the bulk spacer layer has a dielectric constant less than 4.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the bulk spacer layer is a nitrogen free silicon oxycarbide material.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the treated seal spacer layer has a dielectric constant greater than the bulk spacer layer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the treated seal spacer has a film density greater that the bulk spacer layer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the contact etching stop layer is a silicon nitride containing material.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the bulk spacer layer has a thickness greater than the treated seal spacer layer.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the source/drain region extends above the spacer feature.

### Claim 10

A method for forming a semiconductor device, comprising:
forming a seal spacer layer on a substrate by a first atomic layer deposition process using a first processing gases;
plasma treating the seal spacer layer to form a treated seal spacer layer by a second processing gases, wherein the first processing gas is different from the second processing gas;
forming a bulk spacer layer on the seal spacer layer by a second atomic layer deposition process using the first processing gases; and
patterning the treated seal spacer layer and the bulk spacer layer into a gate spacer feature along a sidewall of a gate structure.

### Claim 11 (depends on 10)

The method of claim 10, wherein plasma treating the seal spacer layer further comprises:
forming a plasma in the second processing gases by applying a microwave power to a plasma processing chamber where the substrate is placed.

### Claim 12 (depends on 10)

The method of claim 10, wherein the first processing gas includes a silicon and carbon containing precursor and an oxygen containing precursor.

### Claim 13 (depends on 12)

The method of claim 12, wherein the silicon and carbon containing precursor is a nitrogen free silicon and carbon containing precursor.

### Claim 14 (depends on 12)

The method of claim 12, wherein the oxygen containing precursor comprises water steam.

### Claim 15 (depends on 12)

The method of claim 12, wherein the silicon and carbon containing precursor has a linear Si—C—Si bonding structure.

### Claim 16 (depends on 10)

The method of claim 10, wherein the bulk spacer layer has a thickness greater than the treated seal spacer layer.

### Claim 17 (depends on 10)

The method of claim 10, wherein the second processing gas comprises a hydrogen containing gas, an inert gas, or a combination thereof.

### Claim 18

A method for forming a semiconductor device, comprising:
forming a spacer feature comprising a treated seal spacer layer and a bulk spacer layer along a sidewall of a gate structure on a substrate, wherein the gate structure is formed over an active area comprising a source/drain region on the substrate, the source/drain region being proximate the gate structure; and
removing the gate structure and at least a portion of the treated seal spacer layer from along the sidewall of the gate structure, wherein the gate structure is removed while maintaining the treated seal spacer layer along the source/drain region.

### Claim 19 (depends on 18)

The method of claim 18, wherein removing the gate structure and the at least the portion of the treated seal spacer layer from along the sidewall of the gate structure further comprises:
maintaining the bulk spacer layer along the sidewall of the gate structure and along the source/drain region.

### Claim 20 (depends on 18)

The method of claim 18, wherein the gate structure is a dummy gate structure.