# US 10,483,371 B2 · Semiconductor structure and fabrication method thereof

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- Number: US 10,483,371 B2
- Document ID: US10483371B2
- Status: Granted
- Kind: B2
- Application number: 15/925,974
- Filed: 2018-03-20
- Published: 2018-09-27
- Granted: 2019-11-19
- Earliest claimed: 2017-03-21
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Hao Deng
- Web page: https://patentgrep.com/patent/US10483371B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/511: {for IGFETs}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10W 20/033: {in openings in dielectrics}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure and a fabrication method are provided. The fabrication method includes: providing a substrate; forming a gate dielectric layer on the substrate; forming a dielectric barrier layer structure on the gate dielectric layer, a first silicon source gas being used to dope silicon in the dielectric barrier layer structure; forming a work function layer on the dielectric barrier layer structure; forming a gate barrier layer structure on the work function layer, a second silicon source gas being used to dope silicon in the gate barrier layer structure; and forming a gate electrode layer on the gate barrier layer structure.

## Claims

### Claim 1

A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a gate dielectric layer on the substrate;
forming a dielectric barrier layer structure on the gate dielectric layer, wherein a first silicon source gas is used to dope silicon in the dielectric barrier layer structure;
forming a work function layer on the dielectric barrier layer structure;
forming a gate barrier layer structure on the work function layer, wherein a second silicon source gas is used to dope silicon in the gate barrier layer structure, wherein the dielectric barrier layer structure has a stacked structure and an average atomic percentage concentration of silicon in the dielectric barrier layer structure is smaller than an average atomic percentage concentration of silicon in a layer of the stacked structure adjacent to the work function layer; and
forming a gate electrode layer on the gate barrier layer structure.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the dielectric barrier layer structure includes:
a first dielectric barrier layer doped with silicon on the gate dielectric layer, and
a second dielectric barrier layer on the first dielectric barrier layer.

### Claim 3 (depends on 2)

The method according to claim 2, wherein:
a thickness of the first dielectric barrier layer is in a range of approximately from 20 Å to 40 Å.

### Claim 4 (depends on 2)

The method according to claim 2, wherein:
the first dielectric barrier layer is made of a material including silicon-doped titanium nitride.

### Claim 5 (depends on 2)

The method according to claim 2, wherein:
an atomic percentage concentration of silicon in the first dielectric barrier layer is in a range of approximately 5%-15%.

### Claim 6 (depends on 4)

The method according to claim 4, wherein:
the first dielectric barrier layer structure is formed by an atomic layer deposition process and the first silicon source gas includes trisilylamine;
the atomic layer deposition process includes a reaction gas of the first silicon source gas and a titanium source gas, wherein the first silicon source gas has a flow rate in a range of approximately from 50 standard milliliters/minute to 150 standard milliliters/minute, and the titanium source gas includes TiCl4 with a flow rate in a range of approximately from 100 standard milliliters/minute to 300 standard milliliters/minute;
the atomic layer deposition process further includes a deposition temperature in a range of approximately from 200° C. to 350° C. and a pressure of the reaction chamber in a range of approximately from 2 Torr to 10 Torr.

### Claim 7 (depends on 2)

The method according to claim 2, wherein:
a thickness of the second dielectric barrier layer is in a range of approximately from 10 Å to 20 Å.

### Claim 8 (depends on 2)

The method according to claim 2, wherein:
the second dielectric barrier layer is made of a material including titanium nitride; and
the second dielectric barrier layer is formed by an atomic layer deposition process.

### Claim 9 (depends on 1)

The method according to claim 1, wherein the gate barrier layer structure includes:
a first gate barrier layer on the work function layer, and
a second gate barrier layer on the first gate barrier layer,
wherein the second gate barrier layer is doped with silicon.

### Claim 10 (depends on 9)

The method according to claim 9, wherein:
a thickness of the first gate barrier layer is in a range of approximately from 10 Å to 20 Å.

### Claim 11 (depends on 9)

The method according to claim 9, wherein:
the first gate barrier layer is made of a material including titanium nitride; and
the first gate barrier layer is formed by an atomic layer deposition process.

### Claim 12 (depends on 9)

The method according to claim 9, wherein:
a thickness of the second gate barrier layer is in a range of approximately from 20 Å to 40 Å.

### Claim 13 (depends on 9)

The method according to claim 9, wherein:
the second gate barrier layer is made of a material including silicon-doped titanium nitride.

### Claim 14 (depends on 9)

The method according to claim 9, wherein:
an atomic percentage concentration of silicon in the second gate barrier layer is in a range of approximately 5%-15%.

### Claim 15 (depends on 13)

The method according to claim 13, wherein:
the second gate barrier layer is formed by an atomic layer deposition process, and the second silicon source gas includes trisilylamine;
the atomic layer deposition process includes a reaction gas of the second silicon gas and a titanium source gas, wherein the flow rate of the second silicon source gas is in a range of approximately from 50 standard milliliters/minute to 150 standard milliliters/minute, and the titanium source gas includes TiCl4 with a flow rate in a range of approximately from 100 standard milliliters/minute to 300 standard milliliters/minute; and
the atomic layer deposition process further includes a deposition temperature in a range of approximately from 200° C. to 350° C. and a pressure of the reaction chamber in a range of approximately from 2 Torr to 10 Torr.

### Claim 16 (depends on 1)

The method according to claim 1, wherein:
each of the first and second silicon source gases includes trisilylamine or a combination of trisilylamine and silane.

### Claim 17 (depends on 2)

The method according to claim 2, wherein:
the average atomic percentage concentration of silicon in the dielectric barrier layer structure is smaller than the average atomic percentage concentration of silicon in the first dielectric barrier layer.

### Claim 18 (depends on 9)

The method according to claim 9, wherein:
the gate barrier layer structure have stacked structures, and
an average atomic percentage concentration of silicon in the gate barrier layer structure is smaller than an average atomic percentage concentration of silicon in the second gate barrier layer.