# US 10,483,368 B1 · Single crystalline extrinsic bases for bipolar junction structures

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- Number: US 10,483,368 B1
- Document ID: US10483368B1
- Status: Granted
- Kind: B1
- Application number: 15/979,649
- Filed: 2018-05-15
- Published: 2019-11-21
- Granted: 2019-11-19
- Earliest claimed: 2018-05-15
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Pouya Hashemi; Tak Ning; Jeng-Bang Yau; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US10483368B1

## CPC

- H10D 10/021: {of heterojunction BJTs [HBT]}
- H10D 10/061: {of lateral BJTs (of heterojunction BJTs H10D10/021; of thin film BJTs H10D10/041)}
- H10D 10/60: Lateral BJTs
- H10D 10/80: Heterojunction BJTs
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/134: {of lateral BJTs}
- H10D 62/137: {Collector regions of BJTs}
- H10D 62/184: {of lateral BJTs}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/281: {Base electrodes for bipolar transistors}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3466: {Crystal orientation}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/221: {characterised by the angle between the ion beam and the mask}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10P 52/402: {of semiconductor materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Bipolar junction transistor structures and methods for making the same are provide. The method includes: providing a substrate with an insulator layer and a device layer over the insulator layer, forming an intrinsic base from the device layer, forming emitter and collector regions from the device layer, and after forming i) the intrinsic base and ii) the emitter and collector regions, depositing a single crystalline extrinsic base over the intrinsic base.

## Claims

### Claim 1

A method for forming a bipolar transistor (BJT) structure comprising:
providing a substrate with an insulator layer and a device layer over the insulator layer;
forming an intrinsic base from the device layer;
forming emitter and collector regions from the device layer;
after forming i) the intrinsic base and ii) the emitter and collector regions, depositing a single crystalline extrinsic base over the intrinsic base;
prior to depositing the extrinsic base, forming an inter-layer dielectric (ILD) material over the structure;
forming a dummy base, with a hardmask thereon, over the device layer; and
performing chemical-mechanical planarization (CMP) on the structure to planarize the ILD in relation to the hardmask.

### Claim 2 (depends on 1)

The method of claim 1 further comprising, before depositing the extrinsic base:
forming a plurality of spacers on at least two sidewalls of the dummy base.

### Claim 3 (depends on 2)

The method of claim 2 further comprising, before depositing the extrinsic base:
depositing a dummy layer over the device layer, wherein the dummy layer has a facet associated with each side of the dummy base.

### Claim 4 (depends on 3)

The method of claim 3 further comprising:
recessing the dummy layer, wherein the recessing forms the intrinsic base and each of the emitter and collector regions.

### Claim 5 (depends on 4)

The method of claim 4, wherein forming the emitter and collector regions further comprises:
doping a portion of the intrinsic base utilizing an angled ion implantation process to form one or more implant junctions; and
epitaxially growing emitter and collector layers over each of the emitter and collector regions.

### Claim 6 (depends on 2)

The method of claim 2, wherein depositing the extrinsic base over the intrinsic base comprises:
removing both the hardmask and the dummy base to form an opening for epitaxial deposition of the extrinsic base.

### Claim 7 (depends on 6)

The method of claim 6, wherein forming the extrinsic base the intrinsic base further comprises:
epitaxially growing, via the opening, the single crystalline extrinsic base over the intrinsic base.

### Claim 8 (depends on 6)

The method of claim 6, wherein the intrinsic base and the extrinsic base are in an epitaxial relationship with respect to one another, and wherein the extrinsic base has a wider band-gap than the intrinsic base.

### Claim 9 (depends on 6)

The method of claim 6 further comprising:
forming one or more facets for the extrinsic base during epitaxial growth of the extrinsic base.

### Claim 10

A bipolar junction transistor structure (BJT) comprising:
a substrate;
an intrinsic base comprising a semiconductor material and is disposed over the substrate;
a plurality of spacers over the intrinsic base;
emitter and collector regions present on opposing sides of the intrinsic base;
an inter-layer dielectric (ILD) material over the emitter and collector regions;
a plurality of contacts in contact with each of the emitter and collector regions;
a single crystalline extrinsic base comprising a semiconductor material and is disposed over the intrinsic base, wherein the single crystalline extrinsic base has one or more facets; and
a metal silicide contact comprising a contact area in contact with the extrinsic base, wherein the contact area is determined by the one or more facets.

### Claim 11 (depends on 10)

The structure according to claim 10, wherein all of the one or more facets have one of a i) <111> crystallographic orientation and ii) a <100> crystallographic orientation.

### Claim 12 (depends on 10)

The structure according to claim 10, wherein the extrinsic base contacts a sidewall of each of the plurality of spacers without contacting a lateral side wall of the intrinsic base.

### Claim 13 (depends on 10)

The structure according to claim 10, wherein the semiconductor material of the extrinsic base has a wider band gap than the semiconductor material of the intrinsic base.

### Claim 14 (depends on 13)

The structure according to claim 13, wherein both the extrinsic base and one or more junctions in contact with the intrinsic base are doped with at least one of an n-type dopant and a p-type dopant.

### Claim 15

A bipolar junction transistor structure (BJT) comprising:
a substrate;
an intrinsic base comprising a semiconductor material and is disposed over the substrate;
a plurality of spacers over the intrinsic base;
emitter and collector regions present on opposing sides of the intrinsic base;
a single crystalline extrinsic base comprising a semiconductor material and is disposed over the intrinsic base,
wherein the semiconductor material of the extrinsic base has a wider band gap than the semiconductor material of the intrinsic base,
wherein both the extrinsic base and one or more junctions in contact with the intrinsic base are doped with at least one of an n-type dopant and a p-type dopant,
wherein the intrinsic base is between 1 nm to 15 nm in length,
and wherein the extrinsic base is between 12 nm and 17 nm in length.

### Claim 16 (depends on 15)

The structure according to claim 15, wherein the single crystalline extrinsic base has one or more facets.

### Claim 17 (depends on 16)

The structure according to claim 16, further comprising:
a metal silicide contact having a contact area in contact with the extrinsic base, wherein the contact area is determined by the one or more facets.

### Claim 18 (depends on 15)

The structure according to claim 15, further comprising:
an inter-layer dielectric (ILD) material over the emitter and collector regions; and
a plurality of contacts in contact with each of the emitter and collector regions.