# US 10,483,367 B2 · Vertical gate all around (VGAA) devices and methods of manufacturing the same

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- Number: US 10,483,367 B2
- Document ID: US10483367B2
- Status: Granted
- Kind: B2
- Application number: 15/872,361
- Filed: 2018-01-16
- Published: 2018-05-17
- Granted: 2019-11-19
- Earliest claimed: 2015-02-13
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chia-Hao Chang; Ming-Shan Shieh; Cheng-Long Chen; Chin-Chi Wang; Chi-Wen Liu; Wai-Yi Lien; Chih-Hao Wang
- Web page: https://patentgrep.com/patent/US10483367B2

## CPC

- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate having a doped region;
a spacer layer over the semiconductor substrate;
a protrusion extending from the doped region away from the semiconductor substrate, the protrusion comprising a first source/drain region adjacent the doped region, a channel region disposed over the first source/drain region, and a second source/drain region disposed over the channel region;
a gate stack encircling the channel region of the protrusion, the gate stack being over the spacer layer; and
an epitaxial semiconductor material disposed over a top surface and extending from sidewalls of the second source/drain region of the protrusion, the epitaxial semiconductor material having an octagonal shape in cross-sectional view.

### Claim 2 (depends on 1)

The device of claim 1, wherein the epitaxial semiconductor material comprises a facet adjacent a bottom region of the second source/drain region of the protrusion, and wherein the facet is separated from the sidewalls of the second source/drain region of the protrusion by a distance less than or equal to about 50 nanometers.

### Claim 3 (depends on 2)

The device of claim 2, wherein the facet is inclined at an angle in a range from about 30 degrees to about 60 degrees with respect to a horizontal reference.

### Claim 4 (depends on 1)

The device of claim 1, wherein the epitaxial semiconductor material comprises pure germanium, a group III-V semiconductor material, or a combination thereof.

### Claim 5 (depends on 1)

The device of claim 1, wherein a dopant concentration of the doped region and the epitaxial semiconductor material is in a range from about 1×1019 cm−3 to about 1×1022 cm−3.

### Claim 6 (depends on 1)

The device of claim 1, wherein a dopant concentration of the doped region is greater than a dopant concentration of the epitaxial semiconductor material.

### Claim 7 (depends on 6)

The device of claim 6, wherein the dopant concentration of the doped region is in a range from about 1×1019 cm−3 to about 1×1022 cm−3 and the dopant concentration of the epitaxial semiconductor material is less than about 1×1018 cm−3.

### Claim 8

A device comprising:
a first doped region over a semiconductor substrate, the first doped region having a first conductivity;
a first protrusion extending from the first doped region;
a second doped region laterally adjacent the first doped region, the second doped region having a second conductivity different from the first conductivity;
a second protrusion extending from the second doped region;
an isolation feature disposed between the first doped region and the second doped region, the isolation feature comprising an insulating material;
a first gate stack surrounding a first portion of the first protrusion, wherein a second portion of the first protrusion is free from the first gate stack;
a second gate stack surrounding a first portion of the second protrusion, wherein a second portion of the second protrusion is free from the second gate stack;
a spacer having a first sidewall and a second sidewall, the first sidewall contacting a sidewall of the first gate stack, and the second sidewall contacting a sidewall of the second gate stack;
a first epitaxial semiconductor material surrounding the second portion of the first protrusion, the first epitaxial semiconductor material having a hexagonal shape in top-down view; and
a second epitaxial semiconductor material surrounding the second portion of the second protrusion, the second epitaxial semiconductor material having a hexagonal shape in top-down view.

### Claim 9 (depends on 8)

The device of claim 8, wherein the first epitaxial semiconductor material has the first conductivity and the second epitaxial semiconductor material has the second conductivity.

### Claim 10 (depends on 8)

The device of claim 8, wherein the first protrusion and the second protrusion comprise nanowires, bars, fins, or a combination thereof.

### Claim 11 (depends on 8)

The device of claim 8, wherein the first epitaxial semiconductor material and the second epitaxial semiconductor material have thicknesses in a range from about 1 nm to about 50 nm.

### Claim 12 (depends on 8)

The device of claim 8, further comprising a first drain contact, the first drain contact comprising:
a first drain silicide over the first epitaxial semiconductor material; and
a first conductive layer over the first drain silicide.

### Claim 13 (depends on 8)

The device of claim 8, wherein:
the first protrusion comprises a first source/drain region, a second source/drain region, and a first channel region, wherein the first doped region, the first source/drain region, the second source/drain region have a dopant concentration in a range from about 1×1019 cm−3 to about 1×1022 cm−3 and the first channel region has a dopant concentration of less than about 1×1018 cm−3; and
the second protrusion comprises a third source/drain region, a fourth source/drain region, and a second channel region, wherein the second doped region, the third source/drain region, the fourth source/drain region have a dopant concentration in a range from about 1×1019 cm−3 to about 1×1022 cm−3 and the second channel region has a dopant concentration of less than about 1×1018 cm−3.

### Claim 14 (depends on 8)

The device of claim 8, wherein:
the first protrusion comprises a first source/drain region, a second source/drain region, and a first channel region, wherein the first doped region and the first source/drain region have a dopant concentration in a range from about 1×1019 cm−3 to about 1×1022 cm−3, the first channel region having a dopant concentration of less than about 1×1018 cm−3, and the second source/drain region having a dopant concentration of less than about 1×1018 cm−3; and
the second protrusion comprises a third source/drain region, a fourth source/drain region, and a second channel region, wherein the second doped region and the a third source/drain region have a dopant concentration in a range from about 1×1019 cm−3 to about 1×1022 cm−3, the second channel region having a dopant concentration of less than about 1×1018 cm−3, and the fourth source/drain region having a dopant concentration of less than about 1×1018 cm−3.

### Claim 15

A device, comprising:
a semiconductor substrate having a doped region;
a first protrusion extending from the doped region, the first protrusion comprising a first source/drain region adjacent the doped region, a first channel region disposed over the first source/drain region, and a second source/drain region disposed over the first channel region;
a second protrusion extending from the doped region, the second protrusion comprising a third source/drain region adjacent the doped region, a second channel region disposed over the third source/drain region, and a fourth source/drain region disposed over the second channel region;
a gate stack encircling the first channel region of the first protrusion and the second channel region of the second protrusion;
a first epitaxial semiconductor material disposed over a top surface and extending from sidewalls of the second source/drain region of the first protrusion, the first epitaxial semiconductor material having an octagonal shape in a first cross-sectional plane; and
a second epitaxial semiconductor material disposed over a top surface and extending from sidewalls of the fourth source/drain region of the second protrusion, the second epitaxial semiconductor material having an octagonal shape in the first cross-sectional plane.

### Claim 16 (depends on 15)

The device of claim 15, wherein the first protrusion is adjacent to the second protrusion, and wherein the first epitaxial semiconductor material contacts the second epitaxial semiconductor material.

### Claim 17 (depends on 16)

The device of claim 16, wherein a thickness of the region at which the first epitaxial semiconductor material contacts the second epitaxial semiconductor material in the first cross-sectional plane is in a range from about 1 nm to about 50 nm.

### Claim 18 (depends on 15)

The device of claim 15, wherein the first epitaxial semiconductor material and the second epitaxial material have rectangular shapes in a second cross-sectional plane, the second cross-sectional plane being perpendicular to the first cross-sectional plane.

### Claim 19 (depends on 15)

The device of claim 15, wherein the first epitaxial semiconductor material and the second epitaxial material have hexagonal shapes in a top-down view.

### Claim 20 (depends on 19)

The device of claim 19, wherein the first protrusion is adjacent to the second protrusion, and wherein the first epitaxial semiconductor material contacts the second epitaxial semiconductor material.