# US 10,483,364 B2 · Semiconductor structure and manufacturing method thereof

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- Number: US 10,483,364 B2
- Document ID: US10483364B2
- Status: Granted
- Kind: B2
- Application number: 16/050,747
- Filed: 2018-07-31
- Published: 2018-12-27
- Granted: 2019-11-19
- Earliest claimed: 2015-12-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Che-Cheng Chang; Chih-Han Lin; Horng-Huei Tseng
- Web page: https://patentgrep.com/patent/US10483364B2

## CPC

- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 64/679: {comprising air gaps}
- H10P 50/283: {by chemical means}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/021: {of air gaps}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 10/20: Air gaps
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/46: comprising air gaps
- H10W 20/0765: {the thin functional dielectric layers being temporary, e.g. sacrificial layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, and a conductive plug. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure while leaving a gap between the conductive plug and the spacer.

## Claims

### Claim 1

A method for manufacturing a semiconductor structure, the method comprising:
forming a dielectric layer on at least one gate structure and at least one source drain structure;
forming an opening in the dielectric layer to expose the source drain structure;
forming a protection layer on at least one sidewall of the opening;
forming a conductive plug in the opening, wherein the conductive plug is electrically connected to the source drain structure;
etching back the dielectric layer to expose a sidewall of the protection layer after the forming the conductive plug; and
removing the protection layer after the forming the conductive plug.

### Claim 2 (depends on 1)

The method of claim 1, wherein the opening further exposes at least a portion of at least one spacer on at least one sidewall of the gate structure.

### Claim 3 (depends on 2)

The method of claim 2, wherein the forming the protection layer further forms the protection layer on the portion of the spacer.

### Claim 4 (depends on 2)

The method of claim 2, wherein the forming the protection layer further forms the protection layer on the exposed source drain structure; and
further comprising:
removing at least a portion of protection layer on the source drain structure to expose the source drain structure before the forming the conductive plug.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
forming at least one stop layer on the dielectric layer and the conductive plug.

### Claim 6 (depends on 1)

The method of claim 1, wherein the protection layer is removed by chemical etching.

### Claim 7 (depends on 1)

The method of claim 1, wherein removing the protection layer forms a gap between the conductive plug and a spacer on the gate structure.

### Claim 8 (depends on 7)

The method of claim 7, wherein the gap has a gas therein.

### Claim 9 (depends on 7)

The method of claim 7, wherein the gap is between the conductive plug and the dielectric layer.

### Claim 10 (depends on 1)

The method of claim 1, wherein the conductive plug has a top surface higher than a top surface of the dielectric layer.

### Claim 11

A method comprising:
forming a gate structure over a substrate, the gate structure comprising spacers on sidewalls of a gate electrode and a mask layer over the gate electrode;
forming a source drain structure on the substrate adjacent the gate structure;
forming a first dielectric layer on the gate structure and the source drain structure;
forming an opening in the first dielectric layer to expose the source drain structure;
lining the opening with a second dielectric layer;
patterning the second dielectric layer to expose the source drain structure;
forming a conductive plug on the second dielectric layer in the opening, the conductive plug contacting the source drain structure; and
removing the second dielectric layer between the conductive plug and the gate structure, wherein after removing the second dielectric layer, the conductive plug has a top surface higher than a top surface of the first dielectric layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein the mask layer is coterminous with the gate electrode.

### Claim 13 (depends on 11)

The method of claim 11, wherein removing the second dielectric layer forms a gap between the conductive plug and the gate structure.

### Claim 14 (depends on 13)

The method of claim 13, wherein the gap extends from a top surface of the first dielectric layer to the source drain structure.

### Claim 15 (depends on 13)

The method of claim 13 further comprising:
forming a third dielectric layer over the conductive plug, the gap, and the first dielectric layer.

### Claim 16 (depends on 11)

The method of claim 11 further comprising:
after the forming the conductive plug, etching back the first dielectric layer to expose at least a portion of the second dielectric layer after the forming the conductive plug.

### Claim 17

A method comprising:
forming a first gate structure and a second gate structure over a substrate, the first gate structure being spaced apart from the second gate structure by a first distance;
forming a source drain structure on the substrate and between the first and second gate structures;
forming a first dielectric layer over the first and second gate structures and the source drain structure;
forming a conductive plug contacting the source drain structure, the conductive plug being in the first dielectric layer; and
after forming the conductive plug, forming a gap between the conductive plug and the first and second gate structures, the gap being filled with a gas, wherein after forming the gap, the conductive plug has an upper portion having a first width, the first width being greater than the first distance.

### Claim 18 (depends on 17)

The method of claim 17 further comprising:
forming an opening through the first dielectric layer to expose the source drain structure;
forming a second dielectric layer on sidewalls of the opening, the conductive plug being in the opening; and
etching the second dielectric layer, the etching forming the gap.

### Claim 19 (depends on 18)

The method of claim 18, wherein the gap is between the conductive plug and the first dielectric layer.

### Claim 20 (depends on 17)

The method of claim 17, wherein the upper portion of the conductive plug is wider than a lower portion of the conductive plug.