# US 10,483,363 B2 · Methods of forming a gate contact structure above an active region of a transistor

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- Number: US 10,483,363 B2
- Document ID: US10483363B2
- Status: Granted
- Kind: B2
- Application number: 15/581,105
- Filed: 2017-04-28
- Published: 2018-11-01
- Granted: 2019-11-19
- Earliest claimed: 2017-04-28
- Assignees: Globalfoundries Inc.
- Applicants: GLOBALFOUNDRIES Inc.
- Inventors: Ruilong Xie; Hao Tang; Cheng Chi; Daniel Chanemougame; Lars W. Liebmann; Mark V. Raymond
- Web page: https://patentgrep.com/patent/US10483363B2

## CPC

- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0698: {Local interconnections}
- H10W 20/076: {in via holes or trenches}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

One method includes forming a gate above a semiconductor substrate, the gate comprising a gate structure and a gate cap positioned above the gate structure, forming a conductive source/drain metallization structure adjacent the gate in each of the source/drain regions and forming a recess in each of the conductive source/drain metallization structures. The method further includes forming a spacer structure that comprises recess filling portions that substantially fill the recesses and a portion that extends across the gate cap, wherein a portion of the gate cap is exposed within the spacer structure, forming an insulating material within the spacer structure and on the exposed portion of the gate cap, forming a gate contact opening that exposes a portion of an upper surface of the gate structure and forming a conductive gate contact structure (CB) in the conductive gate contact opening.

## Claims

### Claim 1

A method of forming a conductive gate contact structure (CB) for a transistor comprising a plurality of source/drain regions, the method comprising:
forming a gate above a semiconductor substrate, said gate comprising a gate structure and a gate cap positioned above said gate structure;
forming a conductive source/drain metallization structure adjacent said gate in each of said source/drain regions;
forming a recess in each of said conductive source/drain metallization structures;
after forming said recess in each of said conductive source/drain metallization structures, forming a spacer structure that comprises lower recess filling portions that substantially fill said recesses and an upper portion that extends across and covers a first portion of an upper surface of said gate cap, wherein a second portion of said upper surface of said gate cap is exposed within said spacer structure and wherein said recess filling portions have an upper surface;
forming an insulating material within said spacer structure and on said exposed second portion of said upper surface of said gate cap, wherein said insulating material is positioned on said upper surface of said recess filling portions;
performing at least one etching process to remove a portion of said insulating material and a portion of said gate cap selectively relative to said spacer structure so as to thereby define a gate contact opening that exposes a portion of an upper surface of said gate structure, wherein at least some of said insulating material positioned above said upper surfaces of said recess filling portions of said spacer structure is removed during said at least one etching process; and
forming said conductive gate contact structure (CB) in said gate contact opening, wherein said conductive gate contact structure (CB) is conductively coupled to said gate structure and wherein said conductive gate contact structure (CB) contacts said upper surfaces of said lower recess filling portions of said spacer structure.

### Claim 2 (depends on 1)

The method of claim 1, wherein said conductive source/drain metallization structures comprise a metal silicide region and a metal-containing material.

### Claim 3 (depends on 1)

The method of claim 1, wherein said conductive source/drain metallization structures comprise a front face and wherein forming said recesses comprises removing a portion of said front face of each of said conductive source/drain metallization structures so as to define a recess comprising a bottom surface and a sidewall surface.

### Claim 4 (depends on 1)

The method of claim 1, wherein an entirety of a bottom surface of said conductive gate contact structure (CB) is positioned vertically above an active region of said transistor.

### Claim 5 (depends on 4)

The method of claim 4, wherein an entirety of an upper surface of said conductive gate contact structure (CB) is positioned vertically above said active region of said transistor.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming a conductive source/drain metallization structure adjacent said gate in each of said source/drain regions comprises forming at least a portion of said conductive source/drain metallization structure in a patterned layer of insulating material that has a plurality of patterned openings positioned above said source/drain regions.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming said insulating material within said spacer structure comprises forming an insulating material comprising one of silicon nitride, SiON, SiOCN, SiCO or SiBCN within said spacer structure.

### Claim 8 (depends on 1)

The method of claim 1, wherein forming said insulating material within said spacer structure comprises forming an insulating material comprised of a material that is the same as a material of said gate cap.

### Claim 9

A method of forming a conductive gate contact structure (CB) for a transistor comprising a plurality of source/drain regions, the method comprising:
forming a recess in each of a first and a second conductive source/drain metallization structure that are positioned in said source/drain regions on opposite sides of a gate by removing at least a portion of a front face of each of said first and second conductive source/drain metallization structures, said gate comprising a gate structure and a gate cap positioned above said gate structure;
forming a spacer structure that comprises lower recess filling portions that substantially fill said recesses and an upper portion that extends across said gate cap, wherein a portion of said gate cap is exposed within said spacer structure and wherein said lower recess filling portions have an upper surface;
forming an insulating material within said spacer structure and on said exposed portion of said gate cap, wherein said insulating material is positioned on said upper surface of said lower recess filling portions;
performing at least one etching process to remove a portion of said insulating material and a portion of said gate cap selectively relative to said spacer structure so as to thereby define a gate contact opening that exposes a portion of an upper surface of said gate structure, wherein at least some of said insulating material positioned above said upper surfaces of said lower recess filling portions of said spacer structure is removed during said at least one etching process; and
forming said conductive gate contact structure (CB) in said gate contact opening, wherein said conductive gate contact structure (CB) is conductively coupled to said gate structure and wherein said conductive gate contact structure (CB) contacts said upper surfaces of said recess filling portions of said spacer structure and wherein an entirety of a bottom surface of said conductive gate contact structure (CB) is positioned vertically above an active region of said transistor.

### Claim 10 (depends on 9)

The method of claim 9, wherein an entirety of an upper surface of said conductive gate contact structure (CB) is positioned vertically above said active region of said transistor.

### Claim 11 (depends on 9)

The method of claim 9, wherein said front face of each of said first and second conductive source/drain metallization structures is substantially vertically oriented.

### Claim 12 (depends on 9)

The method of claim 9, wherein said conductive gate contact structure (CB) is formed in direct contact with said portion of said upper surface of said gate structure exposed by said gate contact opening.

### Claim 13 (depends on 1)

The method of claim 1, wherein said first and second conductive source/drain metallization structures each have a substantially vertically oriented front face.

### Claim 14 (depends on 1)

The method of claim 1, wherein said conductive gate contact structure (CB) is formed in direct contact with said portion of said upper surface of said gate structure exposed by said gate contact opening.

### Claim 15

A method of forming a conductive gate contact structure (CB) for a transistor comprising a plurality of source/drain regions, the method comprising:
forming a gate above a semiconductor substrate, said gate comprising a gate structure and a gate cap positioned above said gate structure;
forming a conductive source/drain metallization structure adjacent said gate in each of said source/drain regions, each of said conductive source/drain metallization structures having a front face that is positioned laterally adjacent to a sidewall surface of a first layer of insulating material;
forming a recess in each of said conductive source/drain metallization structures, each of said recesses exposing a portion of a sidewall surface of said first layer of insulating material;
forming a second layer of insulating material above said gate and above said conductive source/drain metallization structures, said second layer of insulating material comprising:
first portions that at least partially fill each of said respective recesses and cover at least part of said exposed portions of said respective sidewall surfaces of said first layer of insulating material; and
a second portion that extends across and covers a first upper surface portion of said gate cap and exposes a second upper surface portion of said gate cap;
forming a third layer of insulating material above said first and second layers of insulating material and above said gate cap, said third layer of insulating material covering said second portion of said upper surface of said gate cap, an upper surface of said first layer of insulating material, an upper surface of said respective first portions of said second layer of insulating material, and a sidewall surface of said second portion of said second layer of insulating material;
forming a gate contact opening that extends through said third layer of insulating material to expose said upper surfaces of said respective first portions of said second layer of insulating material, and extends through said third layer of insulating material and said gate cap to expose a portion of an upper surface of said gate structure, but does not expose any portions of said conductive source/drain metallization structures; and
forming said conductive gate contact structure (CB) in said gate contact opening, wherein said conductive gate contact structure (CB) is conductively coupled to said gate structure and directly contacts said upper surfaces of said respective first portions of said second layer of insulating material.

### Claim 16 (depends on 15)

The method of claim 15, wherein an entirety of a bottom surface of said conductive gate contact structure (CB) is positioned vertically above an active region of said transistor.

### Claim 17 (depends on 16)

The method of claim 16, wherein an entirety of an upper surface of said conductive gate contact structure (CB) is positioned vertically above said active region of said transistor.

### Claim 18 (depends on 15)

The method of claim 15, wherein said front face of each of said conductive source/drain metallization structures is substantially vertically oriented.

### Claim 19 (depends on 15)

The method of claim 15, wherein said conductive gate contact structure (CB) is formed in direct contact with said portion of said upper surface of said gate structure exposed by said gate contact opening.

### Claim 20 (depends on 15)

The method of claim 15, wherein said gate cap is a same material as said third layer of insulating material, and wherein said second layer of insulating material is a different material from said gate cap and said third layer of insulating material.