# US 10,483,359 B2 · Method of fabricating a power semiconductor device

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- Number: US 10,483,359 B2
- Document ID: US10483359B2
- Status: Granted
- Kind: B2
- Application number: 15/663,329
- Filed: 2017-07-28
- Published: 2017-11-16
- Granted: 2019-11-19
- Earliest claimed: 2013-05-16
- Assignees: Infineon Technologies Americas Corp.
- Applicants: Infineon Technologies Americas Corp.
- Inventors: Timothy D. Henson; Kapil Kelkar; Ljubo Radic
- Web page: https://patentgrep.com/patent/US10483359B2

## CPC

- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/028: {of double-diffused metal oxide semiconductor [DMOS] FETs}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/64: Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/516: {the thicknesses being non-uniform}
- H10P 14/40: of conductive or resistive materials
- H10P 50/693: {characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane}
- H10W 10/051: {of isolation region based on field-effect}
- H10W 10/50: Isolation regions based on field-effect
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed is a power device, such as power MOSFET, and method for fabricating same. The device includes an upper trench situated over a lower trench, where the upper trench is wider than the lower trench. The device further includes a trench dielectric inside the lower trench and on sidewalls of the upper trench. The device also includes an electrode situated within the trench dielectric. The trench dielectric of the device has a bottom thickness that is greater than a sidewall thickness.

## Claims

### Claim 1

A method of fabricating a power semiconductor device, said method comprising:
forming a gate trench in a semiconductor substrate, said gate trench including a gate electrode; and
forming a field plate trench structure in said substrate separate from said gate trench, wherein forming said field plate trench structure comprises:
forming an upper trench situated over a lower trench in said substrate, said upper trench being wider than said lower trench and extending deeper into said substrate than said gate trench, a width of said lower trench being greater than one half a width of said upper trench;
forming a trench dielectric in said lower trench and on sidewalls of said upper trench, said trench dielectric filling completely said lower trench; and
forming a field plate electrode within said trench dielectric;
wherein said trench dielectric is formed such that a bottom thickness of said trench dielectric is greater than a sidewall thickness of said trench dielectric on said sidewalls of said upper trench.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a sacrificial layer in said upper trench prior to said forming said lower trench;
etching said sacrificial layer to form spacers on said sidewalls of said upper trench.

### Claim 3 (depends on 2)

The method of claim 2, further comprising removing said spacers after said forming said lower trench.

### Claim 4 (depends on 2)

The method of claim 2, wherein forming said sacrificial layer in said upper trench prior to said forming said lower trench comprises:
isotropically depositing said sacrificial layer over a hard mask dielectric on said substrate and into said upper trench, without filling said upper trench.

### Claim 5 (depends on 2)

The method of claim 2, wherein forming said lower trench in said substrate comprises:
etching into said substrate in a region below said upper trench and unprotected by said spacers, so that a width of said spacers determines a width of said lower trench.

### Claim 6 (depends on 1)

The method of claim 1, wherein said bottom thickness is at least 120% greater than said sidewall thickness.

### Claim 7 (depends on 1)

The method of claim 1, wherein said sidewall thickness tapers from a top to a bottom of said sidewalls.

### Claim 8 (depends on 1)

The method of claim 1, wherein said trench dielectric comprises TEOS.