# US 10,483,358 B2 · Semiconductor cell structure and power semiconductor device

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- Number: US 10,483,358 B2
- Document ID: US10483358B2
- Status: Granted
- Kind: B2
- Application number: 16/068,098
- Filed: 2016-04-01
- Published: 2019-01-24
- Granted: 2019-11-19
- Earliest claimed: 2016-03-08
- Assignees: No. 24 Research Institute of China Electronics Technology Group Corporation
- Applicants: No. 24 Research Institute of China Electronics Technology Group Corporation
- Inventors: Kaizhou Tan; Gangyi Hu; Zhaohuan Tang; Jianan Wang; Yonghui Yang; Yi Zhong; Yang Cao; Yong Liu; Kunfeng Zhu
- Web page: https://patentgrep.com/patent/US10483358B2

## CPC

- H10D 64/115: {Resistive field plates, e.g. semi-insulating field plates}
- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10D 8/045: {of PN junction diodes}
- H10D 8/60: Schottky-barrier diodes
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/665: {having edge termination structures}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/60: Impurity distributions or concentrations
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3456: {Polycrystalline}
- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10P 70/20: {Cleaning during device manufacture}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10P 14/6304: {Formation by oxidation, e.g. oxidation of the substrate}
- H10P 14/6322: {Formation by thermal treatments (formation by plasma treatment H10P14/6319)}
- H10P 50/266: {by vapour etching only}
- H10P 50/283: {by chemical means}
- H10P 52/403: {of conductive or resistive materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor cell structure and power semiconductor device, wherein, the semiconductor cell structure includes: a highly-doped semiconductor material region, an epitaxial layer, a dielectric insulating layer, a semi-insulating material, and an active device region, a deep groove is further etched on the epitaxial layer, the deep groove vertically extends into the highly-doped semiconductor material region, the dielectric insulating layer is formed on a side wall inside the deep groove, and the deep groove is filled with the semi-insulating material. The cell structure can be applied to the power semiconductor device during actual application, the present invention dramatically reduces the difficulty of the process implementation, relaxes the harsh requirements on charge balance, broadens the tolerant charge mismatch percentage by approximately ten times, and also improves the long-term reliability of normal operation of the device cell at the same time.

## Claims

### Claim 1

A semiconductor cell structure, at least comprising:
a highly-doped semiconductor material region (101);
an epitaxial layer (102) formed on the highly-doped semiconductor material region (101);
an active device region (105) formed on the epitaxial layer (102);
the epitaxial layer (102) is provided with a deep groove (109), the deep groove (109) vertically extends into the highly-doped semiconductor material region (101), a dielectric insulating layer (103) is formed on a side wall inside the deep groove (109), the deep groove (109) is filled with a semi-insulating material (104);
an electrode (106) in contact with the semi-insulating material (104) is formed above the semi-insulating material (104), and a bottom portion of the semi-insulating material (104) is in contact with the highly-doped semiconductor material region (101);
wherein, the highly-doped semiconductor material region 101 is N+ type, the epitaxial layer 102 is N− type; when the highly-doped semiconductor material region 101 is P+ type, the epitaxial layer 102 is P− type,
wherein, the bottom portion of the semi-insulating material (104) and a bottom portion of the dielectric insulating layer (103) vertically extend into the highly doped semiconductor material region (101) at a same depth of h;
wherein, a thickness t of the dielectric insulating layer 103 is in a sublinear relationship with the depth h.

### Claim 2 (depends on 1)

The semiconductor cell structure as in claim 1, wherein the highly-doped semiconductor material region (101) and the epitaxial layer (102) are of a same conductive impurity type.

### Claim 3 (depends on 1)

The semiconductor cell structure as in claim 1, wherein resistivity of the semi-insulating material (104) is 1×104Ω·cm to 1×1013Ω·cm.

### Claim 4 (depends on 1)

The semiconductor cell structure as in claim 1, wherein an impurity concentration of the epitaxial layer (102) is higher than an impurity concentration of a drift region corresponding to a parallel-plane junction at a same operating voltage.

### Claim 5 (depends on 1)

The semiconductor cell structure as in claim 1, wherein the dielectric insulating layer (103) is composed of a single layer of dielectric or a plurality of layers of dielectric.

### Claim 6 (depends on 1)

The semiconductor cell structure as in claim 1, wherein an active region low-voltage electrode (107) is formed above the active device region (105) to serve as a low-voltage electrode of the semiconductor cell structure, wherein the highly-doped semiconductor material region (101) correspondingly is a high-voltage electrode of the semiconductor cell structure.

### Claim 7 (depends on 1)

A power semiconductor device, wherein the power semiconductor device comprises the semiconductor cell structure as in claim 1.