# US 10,483,356 B2 · Power semiconductor device with optimized field-plate design

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- Number: US 10,483,356 B2
- Document ID: US10483356B2
- Status: Granted
- Kind: B2
- Application number: 15/906,698
- Filed: 2018-02-27
- Published: 2019-08-29
- Granted: 2019-11-19
- Earliest claimed: 2018-02-27
- Assignees: Siliconix Incorporated
- Applicants: Siliconix Incorporated
- Inventors: Max Shih-kuan Chen; Hao-Che Chien; Loizos Efthymiou; Florin Udrea; Giorgia Longobardi; Gianluca Camuso
- Web page: https://patentgrep.com/patent/US10483356B2

## CPC

- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 64/112: {comprising multiple field plate segments}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/111: {Field plates}
- H10D 64/115: {Resistive field plates, e.g. semi-insulating field plates}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10W 20/43: Layouts of interconnections
- H10W 72/019: {of bond pads}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/602: {Heterojunction gate electrodes for FETs}
- H10W 20/42: Vias, e.g. via plugs
- H10W 72/90: Bond pads, in general
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A power semiconductor device and method for making same are disclosed. The device includes a source bonding pad and a drain bonding pad, a drain metallization structure including a drain field plate connected to the drain bonding pad, and a source metallization structure comprising a source field plate connected to the source bonding pad. At least a portion of at least one of the bonding pads is situated directly over an active area. A dimension of at least one of the field plates varies depending upon the structure adjacent to the field plate.

## Claims

### Claim 1

A semiconductor device comprising:
a source bonding pad;
a drain bonding pad;
a drain metallization structure comprising a drain field plate; and
a source metallization structure comprising a source field plate;
at least a portion of the source bonding pad being situated directly over an active area of the device in a first area of the device;
at least a portion of the drain bonding pad being situated directly over an active area of the device in a second area of the device;
wherein the source field plate has a first dimension positioned in the first area, and a second dimension different from the first dimension positioned in an area of the device other than the first area; and
wherein the drain field plate has a first dimension positioned in the second area, and a second dimension different from the first dimension positioned in an area of the device other than the second area.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the second dimension of the source field plate is positioned in the second area, and wherein the second dimension of the drain field plate is positioned in the first area.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein an area of the device has no bonding pad situated directly over an active area of the device in a third area of the device, wherein the source field plate has a third dimension different from either the first dimension or the second dimension of the source field plate positioned in the third area, and wherein the drain field plate has a third dimension different from either the first dimension or the second dimension of the drain field plate positioned in the third area.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a dimension of at least one of the drain field plate or the source field plate varies continuously.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein the first dimension of the source field plate is larger than the second dimension of the source field plate or the third dimension of the source field plate, and wherein the first dimension of the drain field plate is larger than the second dimension of the drain field plate or the third dimension of the drain field plate.

### Claim 6

A method of making a semiconductor device comprising:
forming a source bonding pad;
forming a drain bonding pad;
forming a drain metallization structure comprising a drain field plate;
forming a source metallization structure comprising a source field plate;
situating at least a portion of the source bonding pad directly over an active area of the device in a first area of the device;
situating at least a portion of the drain bonding pad directly over an active area of the device in a first area of the device; and
positioning a portion of the source field plate having a first dimension in the first area, and positioning a portion of the source field plate having a second dimension different from the first dimension in an area of the device other than the first area; and
positioning a portion of the drain field plate having a first dimension in the second area, and positioning a portion of the drain field plate having a second dimension different from the first dimension in an area of the device other than the second area.

### Claim 7 (depends on 6)

The method of claim 6, further comprising positioning the second dimension of the source field plate in the second area, and positioning the second dimension of the drain field plate in the first area.

### Claim 8 (depends on 7)

The method of claim 7, wherein an area of the device has no bonding pad situated directly over an active area of the device in a third area; wherein the source field plate has a third dimension different from either the first dimension or the second dimension of the source field plate, and further comprising positioning the third dimension of the source field plate in the third area; and wherein the drain field plate has a third dimension different from either the first dimension or the second dimension of the drain field plate, and further comprising positioning the third dimension of the drain field plate in the third area.

### Claim 9 (depends on 6)

The method of claim 6, wherein a dimension of at least one of the drain field plate or the source field plate varies continuously.

### Claim 10 (depends on 8)

The method of claim 8, further comprising forming the first dimension of the source field plate to be larger than the second dimension of the source field plate or the third dimension of the source field plate, and forming the first dimension of the drain field plate to be larger than the second dimension of the drain field plate or the third dimension of the drain field plate.