# US 10,483,355 B2 · Forming non-line-of-sight source drain extension in an NMOS FINFET using n-doped selective epitaxial growth

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,483,355 B2
- Document ID: US10483355B2
- Status: Granted
- Kind: B2
- Application number: 15/792,449
- Filed: 2017-10-24
- Published: 2018-03-08
- Granted: 2019-11-19
- Earliest claimed: 2016-05-11
- Assignees: Applied Materials, Inc.
- Applicants: Applied Materials, Inc.
- Inventors: Matthias Bauer; Hans-Joachim L. Gossmann; Benjamin Colombeau
- Web page: https://patentgrep.com/patent/US10483355B2

## CPC

- H10D 62/80: characterised by the materials
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/834: further characterised by the dopants
- H10P 14/274: {using seed materials}
- H10P 14/3442: {N-type}
- H10P 14/36: {characterised by treatments done before the formation of the materials}
- H10P 50/642: {Chemical etching}
- H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes}
- H10D 30/507: {characterised by inner spacers between adjacent channels}
- H10D 62/8325: {Silicon carbide}
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/3208: {Silicon carbide}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.

## Claims

### Claim 1

A finFET device, comprising:
a semiconductor substrate having a bulk semiconductor region;
a semiconductor fin structure that is disposed on the bulk semiconductor region, the semiconductor fin structure comprising:
a source extension region epitaxially grown on the bulk semiconductor region, the source extension region comprising a first n-type dopant;
a drain extension region epitaxially grown on the bulk semiconductor region, the drain extension region comprising the first n-type dopant;
a first carbon-containing layer that is surrounded by the source extension region and not in direct contact with the bulk semiconductor region;
a second carbon-containing layer that is surrounded by the drain extension region and not in direct contact with the bulk semiconductor region;
a source region comprising a second n-type dopant, wherein the source region is surrounded by the first carbon-containing layer and not in direct contact with the bulk semiconductor region;
a drain region comprising the second n-type dopant, wherein the drain region is surrounded by the second carbon-containing layer and not in direct contact with the bulk semiconductor region; and
a channel region between the source extension region and the drain extension region; and
a gate electrode structure that is formed on a portion of the semiconductor fin structure, the gate electrode structure comprising:
a gate electrode layer;
a first gate spacer formed on a first sidewall of the gate electrode layer and on the source extension region; and
a second gate spacer formed on a second sidewall of the gate electrode layer and on the drain extension region wherein
the first n-type dopant is different than the second n-type dopant,
the first n-type dopant in the source extension region prevents diffusion of the second n-type dopant in the source region to the channel region, and
the first n-type dopant in the drain extension region prevents diffusion of the second n-type dopant in the drain region to the channel region.

### Claim 2 (depends on 1)

The finFET device of claim 1, wherein the semiconductor substrate comprises silicon (Si), the first n-type dopant comprises phosphorus, and the second n-type dopant comprises (As).

### Claim 3 (depends on 1)

The finFET device of claim 1, wherein the semiconductor substrate comprises silicon the first n-type dopant comprises phosphorus, and the second n-type dopant comprises antimony (Sb).

### Claim 4 (depends on 1)

The finFET device of claim 1, wherein the source extension region has a thickness that is less than a thickness of the first gate spacer, and
the drain extension region has a thickness that is less than a thickness of the second gate spacer.

### Claim 5

A nanowire structure, comprising:
a semiconductor substrate having a bulk semiconductor region;
a first silicon-germanium (SiGe) layer that is disposed on the bulk semiconductor region, the first silicon-germanium (SiGe) layer comprising a first silicon-germanium (SiGe) portion and a first internal spacer structure; and
a first silicon (Si) layer that is formed on the first silicon-germanium (SiGe) layer, the first silicon (Si) layer comprising a first silicon (Si) portion that is in direct contact with the first silicon-germanium (SiGe) portion and a first arsenic-doped silicon (Si:As) portion that is formed via a selective epitaxial growth (SEG) within a cavity of the first internal spacer structure.

### Claim 6 (depends on 5)

The nanowire structure of claim 5, further comprising:
a second silicon-germanium (SiGe) layer that is formed on the first silicon (Si) layer, the second silicon-germanium (SiGe) layer comprising a second silicon-germanium (SiGe) portion that is in direct contact with the first silicon (Si) portion and a second internal spacer structure that is in direct contact with the first arsenic-doped silicon (Si:As) portion.

### Claim 7 (depends on 6)

The nanowire structure of claim 6, further comprising:
a second silicon (Si) layer that is disposed on the second silicon-germanium (SiGe) layer, the second silicon (Si) layer comprising a second silicon (Si) portion that is in direct contact with the second silicon-germanium (SiGe) portion and a second arsenic-doped silicon (Si:As) portion that is formed via a SEG on the second internal spacer structure.

### Claim 8 (depends on 5)

The nanowire structure of claim 5, wherein the bulk semiconductor region is formed of a crystalline semiconductor material.

### Claim 9 (depends on 5)

The nanowire structure of claim 5, wherein the first arsenic-doped silicon (Si:As) portion comprises an electrically active concentration of arsenic, wherein such electrically active dopant concentration of arsenic does not exceed about 5×1020 atoms/cm3.

### Claim 10 (depends on 5)

The nanowire structure of claim 5, wherein the first silicon (Si) layer has a deposition thickness of about 2 nm to about 10 nm.

### Claim 11

A nanosheet structure, comprising:
a semiconductor substrate having a bulk semiconductor region;
a silicon-germanium (SiGe) layer that is disposed on the bulk semiconductor region, the silicon-germanium (SiGe) layer comprising a silicon-germanium (SiGe) portion and an internal spacer structure; and
a silicon (Si) layer that is formed on the silicon-germanium (SiGe) layer, the silicon (Si) layer comprising a silicon (Si) portion that is in direct contact with the silicon-germanium (SiGe) portion and an arsenic-doped silicon (Si:As) portion that is formed via a selected epitaxial growth (SEG) within a cavity of the internal spacer structure.