# US 10,483,353 B2 · Transistor including tensile-strained germanium channel

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- Number: US 10,483,353 B2
- Document ID: US10483353B2
- Status: Granted
- Kind: B2
- Application number: 15/778,863
- Filed: 2015-12-24
- Published: 2018-12-13
- Granted: 2019-11-19
- Earliest claimed: 2015-12-24
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Chandra S. Mohapatra; Glenn A. Glass; Anand S. Murthy; Karthik Jambunathan; Willy Rachmady; Gilbert Dewey; Tahir Ghani; Jack T. Kavalieros
- Web page: https://patentgrep.com/patent/US10483353B2

## CPC

- H10D 30/751: {having composition variations in the channel regions}
- H10D 12/021: {of gated diodes, e.g. field-controlled diodes [FCD]}
- H10D 12/211: {Gated diodes}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/798: {being provided in or under the channel regions}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/853: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Techniques are disclosed for forming transistor structures including tensile-strained germanium (Ge) channel material. The transistor structures may be used for either or both of n-type and p-type transistor devices, as tensile-strained Ge has very high carrier mobility properties suitable for both types. Thus, a simplified CMOS integration scheme may be achieved by forming n-MOS and p-MOS devices included in the CMOS device using the techniques described herein. In some cases, the tensile-strained Ge may be achieved by epitaxially growing the Ge material on a group III-V material having a lattice constant that is higher than that of Ge and/or by applying a macroscopic 3-point bending to the die on which the transistor is formed. The techniques may be used to form transistors having planar or non-planar configurations, such as finned configurations (e.g., finFET or tri-gate) or gate-all-around (GAA) configurations (including at least one nanowire).

## Claims

### Claim 1

An integrated circuit comprising:
a substrate;
a first transistor comprising
a first body above the substrate, the first body including tensile-strained semiconductor material that includes germanium,
a first gate structure at least above the first body, the first gate structure including one or more metals, and
a first source region and a first drain region, the first body between the first source and drain regions, the first source and drain regions including semiconductor material and n-type dopant; and
a second transistor comprising
a second body above the substrate, the second body including tensile-strained semiconductor material that includes germanium,
a second gate structure at least above the second body, the second gate structure including one or more metals, and
a second source region and a second drain region, the second body between the second source and drain regions, the second source and drain regions including semiconductor material and p-type dopant.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the tensile-strained semiconductor material included in one or both of the first body or the second body is germanium.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, further comprising a complementary metal-oxide-semiconductor (CMOS) device comprising the first and second transistors.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, wherein the first body is a nanowire or a nanoribbon.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, wherein the second body is a nanowire or a nanoribbon.

### Claim 6 (depends on 1)

The integrated circuit of claim 1, wherein the first body is a fin, the fin between two portions of the first gate structure.

### Claim 7 (depends on 1)

The integrated circuit of claim 1, wherein the first gate structure is around the first body.

### Claim 8 (depends on 1)

A computing system comprising the integrated circuit of claim 1.

### Claim 9 (depends on 1)

The integrated circuit of claim 1, further comprising a layer below the first source and drain regions, the layer also below the second source and drain regions, wherein the layer includes group III-V semiconductor material.

### Claim 10 (depends on 9)

The integrated circuit of claim 9, wherein the layer is also below the first and second bodies.

### Claim 11 (depends on 9)

The integrated circuit of claim 9, wherein the layer extends under the first body and under the second body, wherein the layer is continuous from the first source region to the first drain region and the layer is also continuous from the second source region to the second drain region.

### Claim 12 (depends on 9)

The integrated circuit of claim 9, wherein the group III-V semiconductor material included in the layer includes arsenic.

### Claim 13 (depends on 9)

The integrated circuit of claim 9, wherein the group III-V semiconductor material included in the layer has a higher lattice constant than the semiconductor material included in the first body and/or the second body.

### Claim 14 (depends on 9)

The integrated circuit of claim 9, wherein the layer is a strain-relaxed buffer layer.

### Claim 15 (depends on 9)

The integrated circuit of claim 9, further comprising an additional layer between the first body and the layer, the additional layer including group III-V semiconductor material, the additional layer having a thickness lower than a critical thickness of the group III-V semiconductor material included in the additional layer.

### Claim 16 (depends on 15)

The integrated circuit of claim 15, wherein the semiconductor material included in the additional layer includes a conduction band offset of at least 0.25 millielectronvolts relative to the group III-V semiconductor material included in the first body and/or the second body.

### Claim 17 (depends on 15)

The integrated circuit of claim 15, wherein the group III-V semiconductor material included in the additional layer includes indium or gallium, or both indium and gallium.

### Claim 18 (depends on 9)

The integrated circuit of claim 9, further comprising an additional layer between the layer and an underlying substrate, the additional layer including group III-V semiconductor material.

### Claim 19 (depends on 18)

The integrated circuit of claim 18, wherein the group III-V semiconductor material included in the additional layer includes indium or gallium, or both indium and gallium.