# US 10,483,348 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,348 B2 - Document ID: US10483348B2 - Status: Granted - Kind: B2 - Application number: 15/982,775 - Filed: 2018-05-17 - Published: 2018-11-29 - Granted: 2019-11-19 - Earliest claimed: 2017-05-25 - Assignees: Socionext Inc. - Applicants: Socionext, Inc. - Inventors: Hidetoshi Tanaka - Web page: https://patentgrep.com/patent/US10483348B2 ## CPC - H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions} - H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 84/834: {comprising FinFETs} - H10D 89/811: {using FETs as protective elements} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device has transistors formed on a substrate and including first and second impurity regions of a first conductivity type, a guard ring of a second conductivity type formed on the substrate and surrounding the transistors in a plan view, a wiring formed on and electrically connected to the guard ring, and a ground wiring faulted on the wiring and electrically connected to the wiring and the second impurity region. In a plan view, the transistor includes a first part having a distance that is a first distance from the guard ring, and a second part having a distance that is a second distance shorter than the first distance from the guard ring. In a plan view, the first part is located at a position separated from the ground wiring, and the second part is located at a position overlapping the ground wiring. ## Claims ### Claim 1 A semiconductor device comprising: a substrate; a first transistor which includes a first impurity region of a first conductivity type formed in the substrate, and which includes a second impurity region of the first conductivity type formed in the substrate; a first guard ring of a second conductivity type different from the first conductivity type, formed in the substrate, the first guard ring surrounding the first transistor in a plan view; a first wiring formed on the first guard ring and electrically connected to the first guard ring; and a ground wiring formed on the first wiring, the ground wiring being electrically connected to the first wiring and the second impurity region, wherein the first transistor includes a first part and a second part which are respectively arranged in a first direction in a plan view, the first part of the first transistor is separated with a first distance from the first guard ring in a second direction which is perpendicular to the first direction in a plan view, the second part of the first transistor is separated with a second distance from the first guard ring in the second direction in a plan view, the second distance is shorter than the first distance, the first part is separated from the ground wiring in a plan view, and the second part is overlapped with the ground wiring in a plan view. ### Claim 2 (depends on 1) The semiconductor device as claimed in claim 1, further comprising: a power supply wiring, wherein the first impurity region is electrically connected to the power supply wiring. ### Claim 3 (depends on 1) The semiconductor device as claimed in claim 1, further comprising: a plurality of first vias connecting the first guard ring and the first wiring, wherein a density of the plurality of first vias which are overlapped with the ground wiring in a plan view, along a direction in which the first guard ring extends, is higher than a density of the plurality of first vias which are separated from and not overlapped with the ground wiring in a plan view, along the direction in which the first guard ring extends. ### Claim 4 (depends on 1) The semiconductor device as claimed in claim 1, wherein the first transistor includes a third part, the third part is separated with a third distance from the first guard ring in a plan view, the third distance is shorter than the first distance, and the second part is positioned between the first part and the third part in a plan view. ### Claim 5 (depends on 1) The semiconductor device as claimed in claim 1, wherein distance between the first transistor and the first guard ring increases in steps between the first part and the second part in a plan view. ### Claim 6 (depends on 1) The semiconductor device as claimed in claim 1, wherein the first transistor is a Fin FET (Field-Effect-Transistor) or a nanowire FET. ### Claim 7 A semiconductor device comprising: a substrate; a first transistor, which includes a first impurity region of a first conductivity type formed in the substrate, and which includes a second impurity region of the first conductivity type formed in the substrate; a first guard ring of a second conductivity type different from the first conductivity type, formed in the substrate, the first guard ring surrounding the first transistor in a plan view; a first wiring formed on the first guard ring and electrically connected to the first guard ring; and a power supply wiring formed on the first wiring, the power supply wiring being electrically connected to the first wiring and the first impurity region, wherein the first transistor includes a first part and a second part which are respectively arranged in a first direction in a plan view, the first part of the first transistor is separated with a first distance from the first guard ring in a second direction which is perpendicular to the first direction in a plan view, the second part of the first transistor is separated with a second distance from the first guard ring in the second direction in a plan view, the second distance is shorter than the first distance, the first part is separated from the power supply wiring in a plan view, and the second part is overlapped with the power supply wiring in a plan view. ### Claim 8 (depends on 7) The semiconductor device as claimed in claim 7, further comprising: a plurality of first vias connecting the first guard ring and the first wiring, wherein a density of the plurality of first vias which are overlapped with the power supply wiring in a plan view, along a direction in which the first guard ring extends, is higher than a density of the plurality of first vias which are separated from and not overlapped with the power supply wiring in a plan view, along the direction in which the first guard ring extends. ### Claim 9 (depends on 7) The semiconductor device as claimed in claim 7, wherein the first transistor includes a third part, the third part is separated with a third distance from the first guard ring in a plan view, and the second part is positioned between the first part and the third part. ### Claim 10 (depends on 7) The semiconductor device as claimed in claim 7, wherein distance between the first transistor and the first guard ring increases in steps between the first part and the second part in a plan view. ### Claim 11 (depends on 7) The semiconductor device as claimed in claim 7, wherein the first transistor is a Fin FET (Field-Effect-Transistor) or a nanowire FET. ### Claim 12 A semiconductor device comprising: a substrate; a first transistor which includes a first impurity region of a first conductivity type formed in the substrate, and which includes a second impurity region of the first conductivity type formed in the substrate; a first guard ring of a second conductivity type different from the first conductivity type, formed in the substrate, the first guard ring surrounding the first transistor in a plan view; a first wiring formed on the first guard ring and electrically connected to the first guard ring; a ground wiring formed on the first wiring, the ground wiring being electrically connected to the first wiring and the second impurity region; a second transistor, which includes a third impurity region of the second conductivity type formed in the substrate, and which includes a fourth impurity region of the second conductivity type formed in the substrate; a second guard ring of the first conductivity type formed in the substrate, the second guard ring surrounding the second transistor in a plan view; a second wiring formed on the second guard ring and electrically connected to the second guard ring; and a power supply wiring formed on the second wiring, the power supply wiring being electrically connected to the second wiring and the third impurity region, wherein the first transistor includes a first part and a second part, the first part of the first transistor is separated with a first distance from the first guard ring in a plan view, the second part of the first transistor is separated with a second distance from the first guard ring in a plan view, the second distance is shorter than the first distance, the first part is separated from the ground wiring in a plan view, the second part is overlapped with the ground wiring in a plan view, the second transistor includes a third part and a fourth part, the third part of the second transistor is separated with a third distance from the second guard ring in a plan view, the fourth part of the second transistor is separated with a fourth distance from the second guard ring in a plan view, the fourth distance is shorter than the third distance, the third part is separated from the power supply wiring in a plan view, and the fourth part is overlapped with the power supply wiring in a plan view. ### Claim 13 (depends on 12) The semiconductor device as claimed in claim 12, further comprising: a plurality of first vias connecting the first guard ring and the first wiring, wherein a density of the plurality of first vias which are overlapped with the ground wiring in a plan view, along a direction in which the first guard ring extends, is higher than a density of the plurality of first vias which are separated from and not overlapped with the ground wiring in a plan view, along the direction in which the first guard ring extends. ### Claim 14 (depends on 12) The semiconductor device as claimed in claim 12, further comprising: a plurality of second vias connecting the second guard ring and the second wiring, wherein a density of the plurality of second vias which are overlapped with the power supply wiring in a plan view, along a direction in which the second guard ring extends, is higher than a density of the plurality of second vias which are separated from and not overlapped with the power supply wiring in a plan view, along the direction in which the second guard ring extends. ### Claim 15 (depends on 12) The semiconductor device as claimed in claim 12, further comprising: a plurality of first vias connecting the first guard ring and the first wiring; and a plurality of second vias connecting the second guard ring and the second wiring, wherein a density of the plurality of first vias which are overlapped with the ground wiring in a plan view, along a direction in which the first guard ring extends, is higher than a density of the plurality of first vias which are separated from and not overlapped with the ground wiring in a plan view, along the direction in which the first guard ring extends, and wherein a density of the plurality of second vias which are overlapped with the power supply wiring in a plan view, along a direction in which the second guard ring extends, is higher than a density of the plurality of second vias which are separated from and not overlapped with the power supply wiring in a plan view, along the direction in which the second guard ring extends. ### Claim 16 (depends on 12) The semiconductor device as claimed in claim 12, further comprising: an input and output terminal connected to the first impurity region and the fourth impurity region. ### Claim 17 (depends on 12) The semiconductor device as claimed in claim 12, wherein the first transistor includes a fifth part, the fifth part is separated with a third distance from the first guard ring in a plan view, the third distance is shorter than the first distance, and the second part is positioned between the first part and the fifth part in a plan view. ### Claim 18 (depends on 12) The semiconductor device as claimed in claim 12, wherein distance between the first transistor and the first guard ring increases in steps between the first part and the second part in a plan view, and distance between the second transistor and the second guard ring increases in steps between the third part and the fourth part in a plan view. ### Claim 19 (depends on 12) The semiconductor device as claimed in claim 12, wherein the second transistor includes a sixth part, the sixth part is separated with a sixth distance from the second guard ring in a plan view, and the fourth part is positioned between the third part and the sixth part. ### Claim 20 (depends on 12) The semiconductor device as claimed in claim 12, wherein at least one of the first transistor and the second transistor is a Fin FET (Field-Effect-Transistor) or a nanowire FET.