# US 10,483,347 B2 · Semiconductor device, starter circuit, and switched-mode power-supply circuit

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- Number: US 10,483,347 B2
- Document ID: US10483347B2
- Status: Granted
- Kind: B2
- Application number: 16/046,490
- Filed: 2018-07-26
- Published: 2019-03-14
- Granted: 2019-11-19
- Earliest claimed: 2017-09-11
- Assignees: Fuji Electric Co., Ltd.
- Applicants: Fuji Electric Co., Ltd.
- Inventors: Taichi Karino
- Web page: https://patentgrep.com/patent/US10483347B2

## CPC

- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H02M 1/36: Means for starting or stopping converters
- H02M 3/33523: {with galvanic isolation between input and output of both the power stage and the feedback loop}
- H10D 1/47: Resistors having no potential barriers
- H10D 30/83: FETs having PN junction gate electrodes
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/154: {Dispositions}
- H10D 62/158: {Dispositions}
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/115: {Resistive field plates, e.g. semi-insulating field plates}
- H10D 89/60: Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D 89/601: {for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs}
- H02M 1/0006: {Arrangements for supplying an adequate voltage to the control circuit of converters}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)

## Abstract

A semiconductor device includes a p-type semiconductor substrate; an n-type drift layer on the substrate; an n-type drain region in contact with the drift layer to be provided on the semiconductor substrate at a center of the drift layer; a p-type gate region on the substrate in an outer side of the drift layer, the gate region including U-shaped first and second concave patterns in a planar pattern, each having entrances of the U-shapes located with equal distances from the drain region, the bottoms of the U-shapes protruding toward an outer side of the planar pattern; n-type source regions in an inner side of the first concave patterns, each of the source regions contacts with the drift layer and the gate region; and n-type surge-current guiding-regions in an inner side of the second concave patterns, each of the surge-current guiding-regions contacts with the drift layer and the gate region.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate of a first conductivity type;
a drift layer of a second conductivity type provided on the semiconductor substrate;
a drain region of the second conductivity type in contact with the drift layer to be provided on the semiconductor substrate at a center of the drift layer;
a gate region of the first conductivity type provided on the semiconductor substrate in an outer side of the drift layer, the gate region including U-shaped first and second concave patterns in a planar pattern, each of which having entrances of the U-shapes located with equal distances from the drain region, the bottoms of the U-shapes protruding toward an outer side of the planar pattern;
source regions of the second conductivity type provided in an inner side of the first concave patterns, each of the source regions contacts with the drift layer and the gate region; and
surge-current guiding-regions of the second conductivity type provided in an inner side of the second concave patterns, each of the surge-current guiding-regions contacts with the drift layer and the gate region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein:
each of the second concave patterns is interposed between a pair of the first concave patterns; and
pinch-off occurs at the entrances of the U-shapes of the second concave patterns between the pair of the first concave patterns when a reverse bias is applied to a p-n junction formed between the gate region and the source regions.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein:
each width of the entrances of the U-shapes of the second concave patterns is narrower than each width of the entrances of the U-shapes of the first concave patterns; and
the pinch-off occurs at the entrances of the U-shapes of the second concave patterns earlier than at the entrances of the U-shapes of the first concave patterns when the reverse bias is applied.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein each width of the surge-current guiding-regions measured in a direction vertical to a direction toward the outer side is wider than the width of the entrances of the U-shapes of the second concave patterns.

### Claim 5 (depends on 2)

The semiconductor device of claim 2, further comprising a pinch-off assisting region provided around the entrance of the U-shape of each of the second concave patterns,
wherein an impurity concentration of the pinch-off assisting region is adjusted so that the pinch-off occurs at the entrances of the U-shapes of the second concave patterns earlier than at the entrances of the U-shapes of the first concave patterns when the reverse bias is applied.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein:
the drift layer extends to the inner side of the first concave patterns in the planar pattern, and the drift layer has a lower impurity concentration than the source regions and the surge-current guiding-regions; and
the pinch-off assisting region of second conductivity type is provided at a site between each entrances of the U-shapes of the second concave patterns and each surge-current guiding-region, the pinch-off assisting region has an area larger than an area of the drift layer allocated in the inner side of the first concave patterns and having an impurity concentration lower than or equal to the impurity concentration of the drift layer.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, wherein:
the drift layer extends to the inner side of the first concave patterns and has a lower impurity concentration than the source regions and the surge-current guiding-regions; and
the pinch-off assisting region of second conductivity type is provided at a site between each entrances of the U-shapes of the second concave patterns and each surge-current guiding-region, the length of the pinch-off assisting region measured between the entrances and the surge-current guiding-region is longer than a distance between each entrances of the U-shapes of the first concave patterns and each source region, and the pinch-off assisting region has an impurity concentration lower than or equal to the impurity concentration of the drift layer.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, wherein the pinch-off assisting region is assigned in each of the drift layer extending into to the inner sides of the second concave patterns.

### Claim 9 (depends on 6)

The semiconductor device of claim 6, wherein the pinch-off assisting region is a layer having a lower impurity concentration than the drift layer.

### Claim 10 (depends on 5)

The semiconductor device of claim 5, the pinch-off assisting region of first conductivity type is provided between the drift layer and the gate region at a position corresponding to an inner wall of the respective second concave patterns, the pinch-off assisting region having a higher impurity concentration than the gate region.

### Claim 11 (depends on 5)

The semiconductor device of claim 5, the pinch-off assisting region is provided adjacent to the respective surge-current guiding-regions at an upper portion of the drift layer.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, further comprising:
a gate wire electrically connected to the gate region;
a source wire electrically connected to the respective source regions;
a drain wire electrically connected to the drain layer, and
a surge-current guiding-electrode electrically connected to the respective surge-current guiding-regions.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the gate wire and the surge-current guiding-electrode are connected together.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, wherein the gate wire and the surge-current guiding-electrode are electrically connected to ground potential.

### Claim 15

A starter circuit comprising a semiconductor device, the semiconductor device including:
a semiconductor substrate of a first conductivity type;
a drift layer of a second conductivity type provided on the semiconductor substrate;
a drain region of the second conductivity type in contact with the drift layer to be provided on the semiconductor substrate at a center of the drift layer;
a gate region of the first conductivity type provided on the semiconductor substrate in an outer side of the drift layer, the gate region including U-shaped first and second concave patterns in a planar pattern, each of which having entrances of the U-shapes located with equal distances from the drain region, the bottoms of the U-shapes protruding toward an outer side of the planar pattern;
source regions of the second conductivity type provided in an inner side of the first concave patterns, each of the source regions contacts with the drift layer and the gate region; and
surge-current guiding-regions of the second conductivity type provided in an inner side of the second concave patterns, each of the surge-current guiding-regions contacts with the drift layer and the gate region.

### Claim 16

A switched-mode power-supply circuit comprising a starter circuit having a semiconductor device, the semiconductor device including:
a semiconductor substrate of a first conductivity type;
a drift layer of a second conductivity type provided on the semiconductor substrate;
a drain region of the second conductivity type in contact with the drift layer to be provided on the semiconductor substrate at a center of the drift layer;
a gate region of the first conductivity type provided on the semiconductor substrate in an outer side of the drift layer, the gate region including U-shaped first and second concave patterns in a planar pattern, each of which having entrances of the U-shapes located with equal distances from the drain region, the bottoms of the U-shapes protruding toward an outer side of the planar pattern;
source regions of the second conductivity type provided in an inner side of the first concave patterns, each of the source regions contacts with the drift layer and the gate region; and
surge-current guiding-regions of the second conductivity type provided in an inner side of the second concave patterns, each of the surge-current guiding-regions contacts with the drift layer and the gate region.