# US 10,483,346 B2 · Semiconductor device with support pattern

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- Number: US 10,483,346 B2
- Document ID: US10483346B2
- Status: Granted
- Kind: B2
- Application number: 16/115,690
- Filed: 2018-08-29
- Published: 2019-07-04
- Granted: 2019-11-19
- Earliest claimed: 2018-01-03
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Ki-hyung Nam; Bong-Soo Kim; Yoosang Hwang
- Web page: https://patentgrep.com/patent/US10483346B2

## CPC

- H10D 1/716: {having vertical extensions}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/033: {the capacitor extending over the transistor}
- H10B 12/31: {having a storage electrode stacked over the transistor}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/482: {Bit lines}
- H10B 12/485: {Bit line contacts}
- H10B 12/488: {Word lines}
- H10B 20/00: Read-only memory [ROM] devices
- H10D 64/0113: {the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers}
- H10D 64/20: Electrodes characterised by their shapes, relative sizes or dispositions
- H10P 14/418: {the conductive layers comprising transition metals}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 50/283: {by chemical means}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device including a plurality of pillars on a semiconductor substrate; and a support pattern in contact with some lateral surfaces of the pillars and connecting the pillars with one another, wherein the support pattern includes openings that expose other lateral surfaces of the pillars, each of the pillars includes a first pillar upper portion in contact with the support pattern and a second pillar upper portion spaced apart from the support pattern, and the second pillar upper portion has a concave slope.

## Claims

### Claim 1

A semiconductor device, comprising:
a plurality of pillars on a semiconductor substrate; and
a support pattern in contact with some lateral surfaces of the pillars and connecting the pillars with one another,
wherein:
the support pattern includes openings that expose other lateral surfaces of the pillars,
each of the pillars includes a first pillar upper portion in contact with the support pattern and a second pillar upper portion spaced apart from the support pattern, and
the second pillar upper portion has a concave slope.

### Claim 2 (depends on 1)

The device as claimed in claim 1, wherein a top end of the first pillar upper portion has the same height as that of a top end of the support pattern.

### Claim 3 (depends on 1)

The device as claimed in claim 1, wherein the second pillar upper portion is exposed in a corresponding one of the openings.

### Claim 4 (depends on 1)

The device as claimed in claim 1, wherein a lateral surface of the support pattern and a boundary between the first pillar upper portion and the second pillar upper portion define a planar circle or polygon shape, the lateral surface of the support pattern being exposed to the openings.

### Claim 5 (depends on 1)

The device as claimed in claim 1, wherein:
the support pattern includes a top surface and a bottom surface facing each other, and
a width of the bottom surface is greater than a width of the top surface.

### Claim 6 (depends on 1)

The device as claimed in claim 1, wherein each of the pillars is a bottom electrode and has a plug shape or a cup shape.

### Claim 7 (depends on 6)

The device as claimed in claim 6, further comprising a subsidiary support pattern below the support pattern and in contact with a sidewall of the bottom electrode,
wherein the subsidiary support pattern is spaced apart from the support pattern and has the same planar shape as that of the support pattern.

### Claim 8 (depends on 7)

The device as claimed in claim 7, wherein a top surface of the subsidiary support pattern has a height from the semiconductor substrate that is less than that of a bottom end of the concave slope.

### Claim 9 (depends on 1)

The device as claimed in claim 1, further comprising:
a dielectric layer conformally covering a surface of the support pattern and surfaces of the pillars; and
a top electrode on the dielectric layer.

### Claim 10 (depends on 1)

The device as claimed in claim 1, wherein a bottom surface of the support pattern has a height from the semiconductor substrate that is greater than that of a bottom end of the concave slope.

### Claim 11 (depends on 1)

The device as claimed in claim 1, wherein the concave slope forms a curved surface.

### Claim 12

A semiconductor device, comprising:
a plurality of bottom electrodes on a semiconductor substrate; and
a support pattern in contact with some lateral surfaces of the bottom electrodes and connecting the bottom electrodes with one another,
wherein:
the support pattern includes openings that expose other lateral surfaces of the bottom electrodes, and
each of upper portions of the bottom electrodes has a partially concave slope.

### Claim 13 (depends on 12)

The device as claimed in claim 12, wherein the concave slope forms a curved surface.

### Claim 14 (depends on 12)

The device as claimed in claim 12, wherein a bottom surface of the support pattern has a height from the semiconductor substrate that is greater than that of a bottom end of the concave slope.

### Claim 15

A semiconductor device, comprising:
a plurality of bottom electrodes on a semiconductor substrate; and
a support pattern in contact with some lateral surfaces of the bottom electrodes and connecting the bottom electrodes with one another,
wherein:
the support pattern includes an opening that exposes other lateral surfaces of the bottom electrodes,
each of upper portions of the bottom electrodes has a partially concave slope, and
a bottom surface of the support pattern is farther from the semiconductor substrate than a bottom end of the concave slope.

### Claim 16 (depends on 15)

The device as claimed in claim 15, further comprising a subsidiary support pattern below the support pattern and in contact with sidewalls of the bottom electrodes,
wherein:
the subsidiary support pattern is spaced apart from the support pattern and has the same planar shape as that of the support pattern, and
a top surface of the subsidiary support pattern is closer to the semiconductor substrate than the bottom end of the concave slope.

### Claim 17 (depends on 15)

The device as claimed in claim 15, wherein the concave slope of the bottom electrodes is exposed within the opening.

### Claim 18 (depends on 15)

The device as claimed in claim 15, wherein a top end of the concave slope and a lateral surface of the support pattern define a planar circle or polygon shape, the lateral surface of the support pattern being exposed to the opening.

### Claim 19 (depends on 15)

The device as claimed in claim 15, wherein an interval between upper portions of neighboring bottom electrodes exposed to the opening is greater than an interval between lower portions of the neighboring bottom electrodes.

### Claim 20 (depends on 15)

The device as claimed in claim 15, wherein the concave slope forms a curved surface.