# US 10,483,341 B2 · Display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,341 B2 - Document ID: US10483341B2 - Status: Granted - Kind: B2 - Application number: 15/974,530 - Filed: 2018-05-08 - Published: 2019-03-28 - Granted: 2019-11-19 - Earliest claimed: 2017-09-28 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Kwang Chul Jung; Hyun Joon Kim; Sung Yoon Kim; Hyun Suk Yang; Doo Youl Lee - Web page: https://patentgrep.com/patent/US10483341B2 ## CPC - H10K 59/131: Interconnections, e.g. wiring lines or terminals - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/3225: using an active matrix - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/3275: Details of drivers for data electrodes - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2300/0426: Layout of electrodes and connections - G09G 2310/0281: Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A display device includes first pixels in a first pixel area and coupled with first scan lines, first scan stage circuits in a first peripheral area outside the first pixel area, and configured to supply a first scan signal to the first scan lines, second pixels in a second pixel area having a width that is less than a width of the first pixel area, and coupled with second scan lines, second scan stage circuits in a second peripheral area outside the second pixel area, and configured to generate a second scan signal, and first load matching units respectively between the second scan stage circuits, and configured to delay the second scan signal, and to supply the delayed second scan signal to the second scan lines. ## Claims ### Claim 1 A display device comprising: first pixels in a first pixel area and coupled with first scan lines; first scan stage circuits in a first peripheral area outside the first pixel area, and configured to supply a first scan signal to the first scan lines; second pixels in a second pixel area having a width that is less than a width of the first pixel area, and coupled with second scan lines; second scan stage circuits in a second peripheral area outside the second pixel area, and configured to generate a second scan signal; and first load matching units respectively between the second scan stage circuits, and configured to delay the second scan signal, and to supply the delayed second scan signal to the second scan lines. ### Claim 2 (depends on 1) The display device according to claim 1, wherein at least a corner of the second pixel area has a curved shape. ### Claim 3 (depends on 1) The display device according to claim 1, wherein a number of respective ones of the second pixels on each horizontal line is reduced in a direction away from the first pixel area. ### Claim 4 (depends on 1) The display device according to claim 1, wherein each of the first load matching units comprises: a first delay pattern; and a second delay pattern on a layer that is different from a layer on which the first delay pattern is located, with an insulating layer provided therebetween. ### Claim 5 (depends on 4) The display device according to claim 4, wherein the first delay pattern comprises: an input terminal coupled to an output terminal of a corresponding one of the second scan stage circuits; and an output terminal electrically coupled to a corresponding one of the second scan lines. ### Claim 6 (depends on 4) The display device according to claim 4, wherein the first delay pattern and the second delay pattern form a delay capacitor. ### Claim 7 (depends on 6) The display device according to claim 6, wherein the first load matching units delay the second scan signal by a time constant corresponding to the first delay pattern and the second delay pattern. ### Claim 8 (depends on 7) The display device according to claim 7, wherein the time constant is increased as a distance between the first peripheral area and a corresponding one of the first load matching units is increased. ### Claim 9 (depends on 1) The display device according to claim 1, wherein a distance between the second scan stage circuits is greater than a distance between the first scan stage circuits. ### Claim 10 (depends on 1) The display device according to claim 1, further comprising: third pixels in a third pixel area spaced apart from the second pixel area, and coupled with third scan lines; third scan stage circuits in a third peripheral area provided outside the third pixel area, and configured to generate a third scan signal; and second load matching units respectively between the third scan stage circuits, and configured to delay the third scan signal, and to supply the delayed third scan signal to the third scan lines. ### Claim 11 (depends on 10) The display device according to claim 10, wherein the third pixel area has a width that is less than the width of the first pixel area, and wherein a number of respective ones of the third pixels on each horizontal line is reduced in a direction away from the first pixel area. ### Claim 12 (depends on 10) The display device according to claim 10, wherein a distance between the third scan stage circuits is greater than a distance between the first scan stage circuits. ### Claim 13 (depends on 10) The display device according to claim 10, wherein each of the second load matching units comprises: a first delay pattern; and a second delay pattern on a layer that is different from a layer on which the first delay pattern is located, the second delay pattern being configured to form a capacitance with the first delay pattern. ### Claim 14 (depends on 13) The display device according to claim 13, wherein the second load matching units delay the third scan signal by a time constant corresponding to the first delay pattern and the second delay pattern. ### Claim 15 (depends on 14) The display device according to claim 14, wherein the time constant is increased as a distance between the first peripheral area and a corresponding one of the second load matching units is increased. ### Claim 16 (depends on 1) The display device according to claim 1, further comprising: a first antistatic circuit coupled with the first scan lines; and a second antistatic circuit coupled with the second scan lines.