# US 10,483,324 B2 · 3D vertical memory array cell structures and processes

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,483,324 B2
- Document ID: US10483324B2
- Status: Granted
- Kind: B2
- Application number: 15/360,895
- Filed: 2016-11-23
- Published: 2017-05-25
- Granted: 2019-11-19
- Earliest claimed: 2015-11-24
- Applicants: Fu-Chang Hsu
- Inventors: Fu-Chang Hsu
- Web page: https://patentgrep.com/patent/US10483324B2

## CPC

- H10B 63/845: {the switching components being connected to a common vertical conductor}
- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 53/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 61/10: {comprising components having two electrodes, e.g. diodes or MIM elements}
- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10B 63/24: {of the Ovonic threshold switching type}
- H10N 50/01: Manufacture or treatment
- H10N 50/10: Magnetoresistive devices
- H10N 50/80: Constructional details
- H10N 70/021: {Formation of switching materials, e.g. deposition of layers}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

Three-dimensional vertical memory array cell structures and processes. In an exemplary embodiment, a cell structure includes a word line, a selector layer, and a memory layer. The word line, the selector layer, and the memory layer form a vertical cell structure in which at least one of the selector layer and the memory layer are segmented to form a segment that blocks sneak path leakage current on the word line.

## Claims

### Claim 1

A method for forming a vertical memory structure, comprising:
forming a layer stack comprising word line layers separated by insulator layers;
forming an opening through the layer stack to expose internal surfaces of the word line layers;
depositing a selector material directly on the internal surfaces of the word line layers, wherein the depositing forms segments of the selector material, and wherein each segment is deposited on a corresponding internal surface of a respective word line layer;
depositing a memory material directly on the selector material; and
depositing bit line material directly on the memory material.

### Claim 2 (depends on 1)

The method of claim 1, wherein the depositing of the selector material comprises:
removing portions of the word line layers from the internal surfaces of the word lines to form internal open regions; and
filling the internal open regions with the selector material to form the segments of the selector material.

### Claim 3 (depends on 1)

The method of claim 1, wherein the depositing of the memory material comprises depositing the memory material to form segments of the memory material, and wherein each segment of the memory material is deposited on a respective segment of the selector material.

### Claim 4

A 3D vertical array that includes a plurality of cell structures that block sneak path leakage current, the cell structures formed by performing the operations of:
forming a layer stack comprising word line layers separated by insulator layers;
forming an opening through the layer stack to expose internal surfaces of the word line layers;
depositing a selector material directly on the internal surfaces of the word line layers, wherein the depositing forms segments of the selector material, and wherein each segment is deposited on a corresponding internal surface of a respective word line layer;
depositing a memory material directly on the selector material; and
depositing bit line material directly on the memory material.

### Claim 5 (depends on 4)

The array of claim 4, wherein the depositing of the selector material comprises:
removing portions of the word line layers from the internal surfaces of the word lines to form internal open regions; and
filling the internal open regions with the selector material to form the segments of the selector material.

### Claim 6 (depends on 4)

The array of claim 4, wherein the depositing of the memory material comprises depositing the memory material to form segments of the memory material, and wherein each segment of the memory material is deposited on a respective segment of the selector material.