# US 10,483,322 B2 · Memory device and method for fabricating the same

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- Number: US 10,483,322 B2
- Document ID: US10483322B2
- Status: Granted
- Kind: B2
- Application number: 15/617,019
- Filed: 2017-06-08
- Published: 2018-12-13
- Granted: 2019-11-19
- Earliest claimed: 2017-06-08
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Ching-Pei Hsieh; Hsia-Wei Chen; Yu-Wen Liao
- Web page: https://patentgrep.com/patent/US10483322B2

## CPC

- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/841: {Electrodes}
- H10N 70/883: {Oxides or nitrides}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A memory device includes a first inter-layer dielectric layer, plural conductive features, plural memory structures, a filler, and a second inter-layer dielectric layer. The conductive features are embedded in the first inter-layer dielectric layer. The memory structures are respectively over the conductive features. The filler is in between the memory structures. The second inter-layer dielectric layer is over the filler and the memory structures, and the second inter-layer dielectric layer and the filler form an interface, in which the interface extends from one of the memory structures to another of the memory structures.

## Claims

### Claim 1

A memory device, comprising:
a plurality of transistors;
a first inter-layer dielectric layer over the transistors;
a plurality of first conductive features embedded in the first inter-layer dielectric layer;
a plurality of memory structures respectively over the first conductive features, wherein each of the memory structures has a top electrode, a bottom electrode coupled electrically to a respective one of the first conductive features, and a resistive material layer sandwiched between the top and bottom electrodes;
a filler in between the memory structures; and
a second inter-layer dielectric layer over the filler and the memory structures, the second inter-layer dielectric layer and the filler forming an interface, the interface extending from one of the memory structures to another of the memory structures, wherein the second inter-layer dielectric layer has a first portion over the filler and the memory structures and a second portion around the first portion, and a top surface of the first portion of the second inter-layer dielectric layer is higher than a top surface of the second portion of the second inter-layer dielectric layer.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein a bottom of the interface is in a position lower than a top of said one of the memory structures.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the interface is a curved surface, and curving of the interface begins from said one of the memory structures to said another of the memory structures and is free of a singularity.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein the top surface of the first portion of the second inter-layer dielectric layer is smoother than the curved surface.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the second inter-layer dielectric layer is free of a singularity.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the filler comprises a sidewall in contact with said one of the memory structures, and wherein the sidewall is concave.

### Claim 7 (depends on 1)

The memory device of claim 1, further comprising:
a second conductive feature over the top electrodes of the memory structures, wherein the second conductive feature is in contact with the top surface of the first portion of the second inter-layer dielectric layer and the top surface of the second portion of the second inter-layer dielectric layer.

### Claim 8

A memory device, comprising:
a plurality of transistors;
a first inter-layer dielectric layer over the transistors;
a plurality of first conductive features embedded in the first inter-layer dielectric layer;
a plurality of memory structures above the first inter-layer dielectric layer, wherein each of the memory structures has a top electrode, a bottom electrode coupled electrically to a respective one of the first conductive features, and a resistive material layer sandwiched between the top and bottom electrodes; and
a filler in between the memory structures, the filler having a top surface with edges respectively in contact with the memory structures, wherein at least one of the edges of the top surface of the filler that is in contact with its corresponding memory structure is higher than a top surface of the resistive material layer of the corresponding memory structure.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein the top surface of the filler is free of a singularity.

### Claim 10 (depends on 8)

The memory device of claim 8, wherein the top surface of the filler is a concave surface.

### Claim 11 (depends on 8)

The memory device of claim 8, wherein a bottom of the top surface of the filler is in a position not higher than a top of one of the memory structures.

### Claim 12 (depends on 8)

The memory device of claim 8, further comprising:
a spacer abutting one of the memory structures, wherein the spacer and the filler are made of the same material; and
a second inter-layer dielectric layer on a sidewall of the spacer.

### Claim 13 (depends on 8)

The memory device of claim 8, further comprising:
a second inter-layer dielectric layer; and
a second conductive feature embedded in the second inter-layer dielectric layer and electrically connected to one of the memory structures, wherein the second conductive feature is separated from the filler.

### Claim 14 (depends on 8)

The memory device of claim 8, wherein the at least one of the edges of the top surface of the filler that is in contact with its corresponding memory structure is higher than a top surface of the top electrode of the corresponding memory structure.

### Claim 15

A method for fabricating a memory device, comprising:
forming a first inter-layer dielectric layer over a plurality of transistors;
forming a plurality of memory structures above the first inter-layer dielectric layer, wherein each of the memory structures has a top electrode, a bottom electrode, and a resistive material layer sandwiched between the top and bottom electrodes;
forming a film layer on the memory structures such that the film layer has a recess above a gap between the memory structures, wherein a bottom of the recess of the film layer is above a top surface of the top electrode of at least one of the memory structures;
filling the recess of the film layer with a recess filler; and
etching back the recess filler and the film layer until reaching the memory structures.

### Claim 16 (depends on 15)

The method of claim 15, wherein an etching rate of the recess filler and an etching rate of the film layer during the etching back are substantially the same.

### Claim 17 (depends on 15)

The method of claim 15, wherein the filling the recess comprises forming a flowable material in the recess.

### Claim 18 (depends on 15)

The method of claim 15, wherein the filling the recess comprises a coating process.

### Claim 19 (depends on 15)

The method of claim 15, further comprising:
forming a second inter-layer dielectric layer on a remaining portion of the film layer;
forming a through hole in the second inter-layer dielectric layer to expose at least one of the memory structures; and
forming a conductive feature in the through hole.

### Claim 20 (depends on 15)

The method of claim 15, wherein etching back the recess filler and the film layer is performed such that the recess filler is entirely removed.