# US 10,483,321 B2 · High density memory architecture using back side metal layers

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- Number: US 10,483,321 B2
- Document ID: US10483321B2
- Status: Granted
- Kind: B2
- Application number: 15/575,667
- Filed: 2015-06-02
- Published: 2018-10-04
- Granted: 2019-11-19
- Earliest claimed: 2015-06-02
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Yih Wang; Patrick Morrow
- Web page: https://patentgrep.com/patent/US10483321B2

## CPC

- H10B 61/20: {comprising components having three or more electrodes, e.g. transistors}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/34: {of the vertical channel field-effect transistor type}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 50/10: Magnetoresistive devices
- H10N 50/80: Constructional details
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 2213/71: Three dimensional array
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A microelectronic memory having metallization layers formed on a back side of a substrate, wherein the metallization layers on back side may be used for the formation of source lines and word lines. Such a configuration may allow for a reduction in bit cell area, a higher memory array density, and lower source line and word line resistances. Furthermore, such a configuration may also provide the flexibility to independently optimize interconnect performance for logic and memory circuits.

## Claims

### Claim 1

A microelectronic memory comprising:
a substrate comprising a single material structure, wherein the substrate has a front surface and an opposing back surface,
a source line directly contacting the substrate back surface; and
a memory bitcell transistor on the substrate front surface.

### Claim 2 (depends on 1)

The microelectronic memory of claim 1, wherein the memory bitcell transistor includes at least one source/drain structure formed in the substrate, wherein the source line is electrically connected to the at least one source/drain structure.

### Claim 3 (depends on 2)

The microelectronic memory of claim 2, wherein the source line is electrically connected to the at least one source/drain structure through a deep diffusion contact within the substrate.

### Claim 4 (depends on 1)

The microelectronic memory of claim 1, further including a word line formed on the substrate back surface.

### Claim 5 (depends on 4)

The microelectronic memory of claim 4, further including a word line strap comprising the word line on the substrate back surface electrically connected to a word line within a memory bitcell transistor.

### Claim 6 (depends on 5)

The microelectronic memory of claim 5, wherein the word line on the substrate back surface is electrically connected to a word line within a memory bitcell transistor through a source/drain structure and a deep diffusion contact within the substrate.

### Claim 7 (depends on 1)

The microelectronic memory of claim 1, further comprising a memory cell transistor array on the substrate front surface.

### Claim 8 (depends on 7)

The microelectronic memory of claim 7, wherein the memory cell transistor array comprises a plurality of resistance based memory transistors.

### Claim 9

A microelectronic memory comprising:
a substrate comprising a single material structure, wherein the substrate has a front surface and an opposing back surface,
a word line on the substrate back surface;
a source line positioned between the word line and the substrate; and
a memory bitcell transistor on the substrate front surface.

### Claim 10 (depends on 9)

The microelectronic memory of claim 9, further including a word line strap comprising the word line on the substrate back surface electrically connected to a word line within a memory bitcell transistor.

### Claim 11 (depends on 9)

The microelectronic memory of claim 9, wherein the word line on the substrate back surface is electrically connected to a word line within a memory bitcell transistor through a source/drain structure and a deep diffusion contact within the substrate.

### Claim 12 (depends on 9)

The microelectronic memory of claim 9, further including the source line directly contacting the substrate back surface.

### Claim 13 (depends on 12)

The microelectronic memory of claim 12, wherein the memory bitcell transistor includes at least one source/drain structure formed in the substrate, wherein the source line is electrically connected to the at least one source/drain structure.

### Claim 14 (depends on 13)

The microelectronic memory of claim 13, wherein the source line is electrically connected to the at least one source/drain structure through a deep diffusion contact within the substrate.

### Claim 15 (depends on 9)

The microelectronic memory of claim 9, further comprising a transistor array on the substrate front surface.

### Claim 16 (depends on 15)

The microelectronic memory of claim 15, wherein the transistor array comprises a plurality of resistance based memory transistors.