# US 10,483,313 B2 · Solid-state image sensor and electronic device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,313 B2 - Document ID: US10483313B2 - Status: Granted - Kind: B2 - Application number: 15/981,577 - Filed: 2018-05-16 - Published: 2018-09-13 - Granted: 2019-11-19 - Earliest claimed: 2011-10-07 - Assignees: Sony Corporation - Applicants: Sony Corporation - Inventors: Toshifumi Wakano - Web page: https://patentgrep.com/patent/US10483313B2 ## CPC - H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors - H04N 25/778: comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself - H10F 39/199: {Back-illuminated image sensors} - H10F 39/8027: {Geometry of the photosensitive area} - H10F 39/809: {of hybrid image sensors} - H10F 39/811: {Interconnections} - H10F 39/813: {Electronic components shared by multiple pixels, e.g. one amplifier shared by two pixels} - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract There is provided a solid-state image sensor including a semiconductor substrate in which a plurality of pixels are arranged, and a wiring layer stacked on the semiconductor substrate and formed in such a manner that a plurality of conductor layers having a plurality of wirings are buried in an insulation film. In the wiring layer, wirings connected to the pixels are formed of two conductor layers. ## Claims ### Claim 1 An imaging device comprising: a first chip and a second chip stacked to the first chip, wherein the second chip includes, a plurality of 8-pixel share units, wherein each 8-pixel share unit of the plurality of 8-pixel share units includes: first to fourth photodiode regions sharing a first floating diffusion and fifth to eighth photodiode regions sharing a second floating diffusion, the first to eighth photodiode regions sharing a single amplification transistor and a reset transistor; and a power supply line for supplying a drain of the reset transistor with a power supply voltage, the power supply line including a first line disposed on a first layer and extending along a first direction and a second line disposed on a second layer and extending along a second direction, the first and second lines being coupled to each other and pass through the 8-pixel share unit. ### Claim 2 (depends on 1) The imaging device according to claim 1, wherein the second chip is a sensor chip and the first chip is a logic chip. ### Claim 3 (depends on 2) The imaging device according to claim 2, wherein the logic chip that includes a drive circuit that drives a plurality of transistors on the logic chip. ### Claim 4 (depends on 1) The imaging device according to claim 1, wherein the amplification transistor and the reset transistor are located at different positions from each other in the first direction. ### Claim 5 (depends on 4) The imaging device according to claim 4, wherein the first to eighth photodiode regions share a selection transistor. ### Claim 6 (depends on 5) The imaging device according to claim 5, wherein the selection transistor and the reset transistor are located at different positions from each other in the first direction. ### Claim 7 (depends on 5) The imaging device according to claim 5, wherein the first to fourth photodiode regions are located in a first area, wherein the fifth to eight photodiode regions are located in a second area, and wherein the selection transistor is located between the first and second areas. ### Claim 8 (depends on 1) The imaging device according to claim 1, further comprising: first to fourth transfer gate electrodes coupled to the first to fourth photodiode regions respectively, the first to fourth transfer gate electrodes coupled to and arranged around the first floating diffusion; and fifth to eighth transfer gate electrodes coupled to the fifth to eighth photodiode regions respectively, the fifth to eighth transfer gate electrodes coupled to and arranged around the second floating diffusion. ### Claim 9 (depends on 8) The imaging device according to claim 8, wherein the first to fourth transfer gate electrodes are arranged so as to be line-symmetrical in the first direction and the second direction about the first floating diffusion, and the fifth to eighth transfer gate electrodes are arranged so as to be line-symmetrical in the first direction and the second direction about the second floating diffusion. ### Claim 10 (depends on 9) The imaging device according to claim 9, wherein each shape of the first to fourth transfer gate electrodes is substantially triangular, and wherein each shape of the fifth to eighth transfer gate electrodes is substantially triangular. ### Claim 11 (depends on 10) The imaging device according to claim 10, wherein a first outline of the first to fourth transfer gate electrodes and a second outline of the fifth to eighth transfer gate electrodes are substantially quadrangular. ### Claim 12 (depends on 1) The imaging device according to claim 1, wherein the first to fourth photodiode regions are located in a first area, wherein the fifth to eight photodiode regions are located in a second area, and wherein the amplification transistor is located between the first and second areas. ### Claim 13 (depends on 1) The imaging device according to claim 1, wherein first to eighth photodiode regions are coupled to first to eighth transfer lines respectively extending along the second direction. ### Claim 14 (depends on 1) The imaging device according to claim 1, wherein the reset transistor is coupled to a reset line extending along the second direction. ### Claim 15 (depends on 1) The imaging device according to claim 1, wherein the selection transistor is coupled to a select line extending along the first direction. ### Claim 16 (depends on 1) The imaging device according to claim 1, wherein the amplification transistor is coupled to a signal line extending along the second direction. ### Claim 17 (depends on 16) The imaging device according to claim 16, wherein the logic chip includes a column circuit coupled to the signal line that performs correlated double sampling of a signal, and converts the signal to a digital signal. ### Claim 18 (depends on 17) The imaging device according to claim 17, wherein the logic chip includes a digital processing circuit that receives and processes the digital signal. ### Claim 19 (depends on 18) The imaging device according to claim 18, wherein the logic chip includes a memory that stores a processed digital signal received from the digital processing circuit. ### Claim 20 An electronic apparatus, comprising: an imaging device comprising: a first chip and a second chip stacked to the first chip, the second chip having a first side as a light-incident side and a second side bonded to the first chip, wherein the second chip includes, a plurality of 8-pixel share units, wherein each 8-pixel share unit of the plurality of 8-pixel share units includes: first to fourth photodiode regions sharing a first floating diffusion and fifth to eighth photodiode regions sharing a second floating diffusion, the first to eighth photodiode regions sharing a single amplification transistor and a reset transistor; and a power supply line for supplying a drain of the reset transistor with a power supply voltage, the power supply line including a first line disposed on a first layer and extending along a first direction and a second line disposed on a second layer and extending along a second direction, the first and second lines being coupled to each other and pass through the 8-pixel share unit.