# US 10,483,296 B2 · TFT and manufacturing method thereof, array substrate and manufacturing method thereof, and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,296 B2 - Document ID: US10483296B2 - Status: Granted - Kind: B2 - Application number: 15/300,362 - Filed: 2015-10-19 - Published: 2017-06-29 - Granted: 2019-11-19 - Earliest claimed: 2015-06-08 - Assignees: Boe Technology Group Co., Ltd. - Applicants: BOE Technology Group Co., Ltd. - Inventors: Wei Yang; Xiang Liu - Web page: https://patentgrep.com/patent/US10483296B2 ## CPC - H10D 86/0231: {using masks, e.g. half-tone masks} - H10D 30/031: {of thin-film transistors [TFT]} - H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate} - H10D 30/0316: {of lateral bottom-gate TFTs comprising only a single gate} - H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon} - H10D 30/6743: {Silicon} - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 64/514: {characterised by the insulating layers} - H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies} - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/60: wherein the TFTs are in active matrices - H10D 99/00: Subject matter not provided for in other groups of this subclass - H10P 30/202: {characterised by the semiconductor materials} - H10P 30/21: {of electrically active species} - H10P 30/22: using masks - G02F 1/136286: {Wiring, e.g. gate line, drain line} - G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} - G02F 2201/121: common or background - G02F 2201/123: pixel - H10K 59/1201: {Manufacture or treatment} - H10K 59/1213: {the pixel elements being TFTs} - H10K 59/131: Interconnections, e.g. wiring lines or terminals - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES ## Abstract A thin-film transistor (TFT) and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device are disclosed. The manufacturing method of a TFT includes: forming an active layer, a gate electrode, a source electrode and a drain electrode respectively electrically connected with the active layer, and a gate insulating layer disposed between the gate electrode and the active layer, so that the gate electrode, the source electrode and the drain electrode are formed in the same patterning process. The method can reduce the number of masks used in the manufacturing process of the TFT or an array substrate, reduce the technology process, improve the productivity, and reduce the production cost. ## Claims ### Claim 1 An array substrate, comprising a thin-film transistor (TFT) disposed on a base substrate, wherein the TFT includes: an active layer; a gate electrode, a source electrode, and a drain electrode respectively electrically connected with the active layer; and a gate insulating layer disposed between the gate electrode and the active layer, wherein the gate electrode, the source electrode, and the drain electrode are formed by a same film layer, and wherein materials of the gate electrode, the source electrode, and the drain electrode are the same, wherein the gate insulating layer, the gate electrode, the source electrode, and the drain electrode are formed in a same pattering process, and the same patterning process is performed using a single mask. ### Claim 2 (depends on 1) The array substrate according to claim 1, further comprising a plurality of first signal lines extended along a first direction and a plurality of second signal lines extended along a second direction and insulated from the first signal lines, wherein each first signal line includes a plurality of spaced linear portions and connecting portions for connecting adjacent linear portions; the connecting portions and the linear portions are arranged in different layers; the linear portions and the second signal lines are arranged in a same layer; and the first signal lines are gate lines and the second signal lines are data lines; or the first signal lines are data lines and the second signal lines are gate lines. ### Claim 3 (depends on 1) The array substrate according to claim 1, wherein the gate insulating layer is disposed on the active layer; and the gate electrode, the source electrode, and the drain electrode are disposed on the gate insulating layer. ### Claim 4 (depends on 3) The array substrate according to claim 3, wherein the gate insulating layer includes a first insulating portion, a second insulating portion, and a third insulating portion, which are spaced from each other; the first insulating portion is disposed between the source electrode and the active layer; the second insulating portion is disposed between the gate electrode and the active layer; and the third insulating portion is disposed between the drain electrode and the active layer. ### Claim 5 (depends on 4) The array substrate according to claim 4, wherein a first opening is disposed between the first insulating portion and the second insulating portion; a second opening is disposed between the second insulating portion and the third insulating portion; and a width of the active layer is equal to a sum of widths of the first insulating portion, the first opening, the second insulating portion, the second opening, and the third insulating portion, in a direction parallel to the base substrate. ### Claim 6 (depends on 4) The array substrate according to claim 4, wherein the source electrode is electrically connected with the active layer through a first conductive structure, wherein the first conductive structure makes contact with an upper surface of the source electrode and a part of an upper surface of the active layer; and the drain electrode is electrically connected with the active layer through a second conductive structure, wherein the second conductive structure makes contact with an upper surface of the drain electrode and another part of the upper surface of the active layer. ### Claim 7 (depends on 6) The array substrate according to claim 6, further comprising: a pixel electrode electrically connected with the drain electrode and a common electrode arranged in different layers from the pixel electrode, wherein the first conductive structure, the second conductive structure, and the pixel electrode are formed in a same one process and made from a same material, or the first conductive structure, the second conductive structure, and the common electrode are formed in a same one process and made from a same material. ### Claim 8 (depends on 1) The array substrate according to claim 1, wherein the gate insulating layer is disposed on the gate electrode, the source electrode, and the drain electrode; and the active layer is disposed on the gate insulating layer. ### Claim 9 (depends on 1) The array substrate according to claim 1, wherein the source electrode and the drain electrode make contact with the active layer. ### Claim 10 (depends on 9) The array substrate according to claim 9, wherein the gate insulating layer is provided with via holes respectively corresponding to the source electrode and the drain electrode; and the source electrode and the drain electrode respectively make contact with the active layer through the via holes; or the source electrode and the drain electrode are lapped and connected to the active layer. ### Claim 11 (depends on 1) A display device, comprising the array substrate according to claim 1. ### Claim 12 A method for manufacturing a thin film transistor (TFT), comprising: forming an active layer, and a gate electrode, a source electrode, and a drain electrode respectively electrically connected with the active layer, and forming a gate insulating layer disposed between the gate electrode and the active layer, wherein the gate electrode, the source electrode, and the drain electrode are formed by a same film layer, and wherein materials of the gate electrode, the source electrode, and the drain electrode are the same, wherein the gate insulating layer, the gate electrode, the source electrode, and the drain electrode are formed in a same patterning process, and the same patterning process is performed using a single mask. ### Claim 13 (depends on 12) The method according to claim 12, wherein the active layer, the gate insulating layer, the gate electrode, the source electrode, and the drain electrode are formed in the same patterning process by a half-tone mask. ### Claim 14 (depends on 13) The method according to claim 13, wherein the active layer, the gate insulating layer, the gate electrode, the source electrode, and the drain electrode are formed by a first patterning process; a surface of the active layer not covered by the gate insulating layer is subjected to ion implantation or plasma treatment; and a first conductive structure for electrically connecting the source electrode and the active layer, and a second conductive structure for electrically connecting the drain electrode and the active layer, are formed by a second patterning process. ### Claim 15 (depends on 12) The method according to claim 12, wherein the active layer is formed by a first patterning process; the gate insulating layer, and the gate electrode, the source electrode, and the drain electrode, disposed on the gate insulating layer, are formed on the active layer by a second patterning process; at least part of a surface of the active layer not covered by the gate insulating layer is subjected to ion implantation or plasma treatment; and a first conductive structure for electrically connecting the source electrode and the active layer, and a second conductive structure for connecting the drain electrode and the active layer, are formed by a third patterning process. ### Claim 16 (depends on 12) A method for manufacturing an array substrate, comprising: forming a thin film transistor (TFT) on a base substrate, wherein the TFT is manufactured by the method according to claim 12. ### Claim 17 (depends on 16) The method according to claim 16, further comprising: forming a pixel electrode electrically connected with the drain electrode, and forming a common electrode arranged in a different layer from the pixel electrode, wherein the active layer, the gate insulating layer, the gate electrode, the source electrode, and the drain electrode are formed by a first patterning process; a surface of the active layer not covered by the gate insulating layer is subjected to ion implantation or plasma treatment; and the pixel electrode or the common electrode, a first conductive structure for electrically connecting the source electrode and the active layer, and a second conductive structure for connecting the drain electrode and the active layer, are formed by a second patterning process. ### Claim 18 A method for manufacturing a thin film transistor (TFT), comprising: forming an active layer, and a gate electrode, a source electrode, and a drain electrode respectively electrically connected with the active layer, and forming a gate insulating layer disposed between the gate electrode and the active layer, wherein the gate electrode, the source electrode, and the drain electrode are formed in a same patterning process and wherein materials of the gate electrode, the source electrode, and the drain electrode are the same, wherein the active layer is formed by a first patterning process; the gate insulating layer is formed on the active layer by a second patterning process, and via holes through which the active layer is exposed are formed at positions of the gate insulating layer respectively corresponding to the source electrode and the drain electrode; and the source electrode, the gate electrode, and the drain electrode are formed on the gate insulating layer by a third patterning process, so that the source electrode and the drain electrode are respectively electrically connected with the active layer through the via holes; or the source electrode, the gate electrode, and the drain electrode are formed by a first patterning process; the gate insulating layer is formed by a second patterning process, and via holes through which the source electrode and the drain electrode are respectively exposed are formed at positions of the gate insulating layer respectively corresponding to the source electrode and the drain electrode; and the active layer is formed on the gate insulating layer by a third patterning process, so that the active layer is respectively electrically connected with the source electrode and the drain electrode through the via holes.