# US 10,483,292 B2 · Array substrate and display panel

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- Number: US 10,483,292 B2
- Document ID: US10483292B2
- Status: Granted
- Kind: B2
- Application number: 15/660,999
- Filed: 2017-07-27
- Published: 2018-02-01
- Granted: 2019-11-19
- Earliest claimed: 2016-07-28
- Assignees: Boe Technology Group Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.
- Inventors: Chunping Long; Hongfei Cheng
- Web page: https://patentgrep.com/patent/US10483292B2

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/443: {adapted for preventing breakage, peeling or short circuiting}
- H10D 89/811: {using FETs as protective elements}
- H10D 89/931: {characterised by the dispositions of the protective arrangements}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure provides an array substrate and a display device. The array substrate includes a plurality of signal lines, a plurality of secondary discharging lines arranged substantially parallel to each other, each of the plurality secondary discharging being arranged to cross the plurality of signal lines, a plurality of first electrostatic discharging units arranged in one-to-one correspondence with the plurality of signal lines, and a primary discharging line connected to the plurality of secondary discharging lines. One end of each first electrostatic discharging unit is connected to its corresponding signal line, and the other end thereof is connected to one of the plurality of secondary discharging lines.

## Claims

### Claim 1

An array substrate, comprising:
a plurality of signal lines;
a plurality of secondary discharging lines arranged substantially parallel to each other, each of the plurality of secondary discharging lines being arranged to cross the plurality of signal lines;
a plurality of first electrostatic discharging units arranged in one-to-one correspondence with the plurality of signal lines and arranged at an identical side of an entirety of the plurality of secondary discharging lines; and
a primary discharging line connected to the plurality of secondary discharging lines,
wherein a first end of each of the plurality of first electrostatic discharging units is connected to a corresponding signal line of the plurality of signal lines, and a second end of the each of the plurality of first electrostatic discharging units is connected to one of the plurality of secondary discharging lines,
each first electrostatic discharging unit of the plurality of first electrostatic discharging units comprises a first thin film transistor (TFT), a second TFT, and a third TFT;
a gate electrode and a source electrode of the first TFT are short-circuited and connected to one of the plurality of signal lines corresponding to the each first electrostatic discharging unit, and a drain electrode of the first TFT is connected to a source electrode of the second TFT and a gate electrode of the third TFT;
a gate electrode and a drain electrode of the second TFT are short-circuited and connected to the one of the plurality secondary discharging lines corresponding to the each first electrostatic discharging unit;
a source electrode of the third TFT is directly connected to the one of the plurality of signal lines, and a drain electrode of the third TFT is directly connected to the one of the plurality of secondary discharging lines; and
an extension portion of the one of the plurality of signal line corresponding to the each first electrostatic discharging unit is formed into the source electrode of the first TFT and the source electrode of the third TFT, the source electrode of the first TFT is connected to the gate electrode of the first TFT through a first via-hole, an active region of the first TFT is formed above the gate electrode of the first TFT, and the source electrode and the drain electrode of the first TFT are in direct contact with the active region of the first TFT so as to form a source region and a drain region of the first TFT.

### Claim 2 (depends on 1)

The array substrate according to claim 1, wherein two of the plurality of first electrostatic discharging units connected to two adjacent signal lines of the plurality of signal lines respectively are connected to different ones of the plurality of secondary discharging lines.

### Claim 3 (depends on 2)

The array substrate according to claim 2, wherein a quantity of the plurality of secondary discharging lines is smaller than or equal to a quantity of the plurality of signal lines;
N signal lines from an (n*N+1)th signal line to an ((n+1)*N)th signal line among the plurality of signal lines are connected to different ones of the plurality of secondary discharging lines through ones of the plurality of first electrostatic discharging units corresponding respectively to the N signal lines, and an ith signal line and a (z*N+i)th signal line among the plurality of signal lines are connected to a same secondary discharging line of the plurality of secondary discharging lines;
wherein N is the quantity of the plurality of secondary discharging lines and is an integer greater than or equal to 2, n is an integer greater than or equal to 0, z is a positive integer, and i is a positive integer ranging from 1 to N.

### Claim 4 (depends on 3)

The array substrate according to claim 3, wherein there are three secondary discharging lines.

### Claim 5 (depends on 4)

The array substrate according to claim 4, wherein the quantity of the secondary discharging lines is the same as a quantity of subpixels of each pixel on the array substrate.

### Claim 6 (depends on 4)

The array substrate according to claim 4, wherein each pixel on the array substrate comprises a red subpixel, a green subpixel and a blue subpixel; and
the plurality of signal lines comprises a first signal line configured to provide a signal to the red subpixel, a second signal line configured to provide a signal to the green subpixel and a third signal line configured to provide a signal to the blue subpixel, wherein the first signal line, the second signal line, and the third signal line are connected to the three secondary discharging lines respectively through respective ones of the plurality of first electrostatic discharging units.

### Claim 7 (depends on 1)

The array substrate according to claim 1, wherein a protrusion of the one of the plurality of secondary discharging lines is formed into the gate electrode of the second TFT, the source electrode of the second TFT is connected to the drain electrode of the first TFT through a connection line of a metal layer, an extension portion of the metal layer partially overlaps the one of the plurality of secondary discharging lines, the gate electrode of the second TFT is electrically connected to the extension portion of the metal layer through a second via-hole, the extension portion of the metal layer is formed into the drain electrode of the second TFT and the drain electrode of the third TFT, the source electrode and the drain electrode of the second TFT are in direct contact with an active region of the second TFT above the gate electrode of the second TFT so as to form a source region and a drain region of the second TFT, and the source electrode and the drain electrode of the third TFT are in direct contact with an active region of the third TFT above the gate electrode of the third TFT so as to form a source region and a drain region of the third TFT.

### Claim 8 (depends on 1)

The array substrate according to claim 1, wherein a first end of each of the plurality of secondary discharging lines is connected via a second electrostatic discharging unit to the primary discharging line, and a second end of the each of the plurality of secondary discharging lines is arranged in a floating state.

### Claim 9 (depends on 1)

The array substrate according to claim 1, wherein the primary discharging line is a common electrode line.

### Claim 10 (depends on 1)

The array substrate according to claim 1, wherein the plurality of signal lines comprises one of or any combination of: a data signal line, a gate signal line, a control signal line, a clock signal line and a testing signal line.

### Claim 11 (depends on 1)

A display device comprising the array substrate according to claim 1.

### Claim 12 (depends on 1)

The array substrate according to claim 1, wherein two via-holes are formed above the source electrode and the gate electrode of the first TFT, respectively, and a third transparent conductive layer is formed at the two via-holes, and the source electrode and the gate electrode of the first TFT are electrically connected to each other through the third transparent conductive layer.

### Claim 13 (depends on 8)

The array substrate according to claim 8, wherein the second electrostatic discharging unit comprises a fourth TFT and a fifth TFT,
a gate electrode and a source electrode of the fourth TFT are short-circuited and connected to the each of the plurality of secondary discharging lines, and a drain electrode of the fourth TFT is connected to primary discharging line or connected to a source electrode or a drain electrode of any other TFT in the second electrostatic discharging unit;
a gate electrode and a drain electrode of the fifth TFT are short-circuited and connected to the primary discharging line, and a source electrode of the fifth TFT is connected to the each of the plurality secondary discharging lines or connected to a source electrode or a drain electrode of any other TFT in the second electrostatic discharging unit.

### Claim 14 (depends on 13)

The array substrate according to claim 13, wherein the drain electrode of the fourth TFT is connected to the source electrode of the fifth TFT,
the second electrostatic discharging unit further comprises a sixth TFT, a gate electrode of the sixth TFT is connected to the drain electrode of the fourth TFT, a source electrode of the sixth TFT is connected to the each of the plurality of secondary discharging line, and a drain electrode of the sixth TFT is connected to the primary discharging line.

### Claim 15 (depends on 7)

The array substrate according to claim 7, wherein, the gate electrode of the third TFT is electrically connected to the connection line of the metal layer through a third via-hole.