# US 10,483,287 B1 · Double gate, flexible thin-film transistor (TFT) complementary metal-oxide semiconductor (MOS) (CMOS) circuits and related fabrication methods

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- Number: US 10,483,287 B1
- Document ID: US10483287B1
- Status: Granted
- Kind: B1
- Application number: 16/138,084
- Filed: 2018-09-21
- Granted: 2019-11-19
- Earliest claimed: 2018-09-21
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Xia Li; Bin Yang; Gengming Tao
- Web page: https://patentgrep.com/patent/US10483287B1

## CPC

- H10D 86/411: {characterised by materials, geometry or structure of the substrates}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 30/6733: {Multi-gate TFTs}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/0212: {comprising manufacture, treatment or coating of substrates}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Transistors formed on semiconductor substrates are not well-suited for integrated circuits employed in media designed to structurally flex to conform to a shaped surface or in response to physical stress. Structural flexing of wearable electronic devices, such as clothing, may cause cracking in the semiconductor substrate, resulting in failure of the integrated circuits. TFTs formed on flexible substrates can withstand structural flexing without failure. CMOS circuits are employed due to cost, performance, and power efficiency considerations. To provide increased drive strength for such applications, a flexible TFT structure for a CMOS circuit disclosed herein includes an exemplary NFET integrated with a complementary PFET on a flexible substrate. By forming a top gate on a semiconductor layer of a FET opposite to a bottom gate formed between the semiconductor layer and the flexible substrate, an effective thickness of an inversion channel layer induced in the semiconductor layer is doubled.

## Claims

### Claim 1

A complementary metal-oxide semiconductor (CMOS) circuit, comprising:
a flexible substrate;
at least one P-type Field-Effect Transistor (FET) (PFET) formed on a first surface of the flexible substrate, each of the at least one PFET comprising:
a first gate disposed on the first surface of the flexible substrate;
a P-type thin-film semiconductor structure disposed over the first gate in a first axis direction, the P-type thin-film semiconductor structure comprising a first source/drain region, a second source/drain region, and a first channel region between the first and second source/drain regions; and
a second gate disposed over the P-type thin-film semiconductor structure in the first axis direction opposite to the first gate;
at least one N-type FET (NFET) formed on the first surface of the flexible substrate, each of the at least one NFET comprising:
a third gate disposed on the first surface of the flexible substrate;
an N-type thin-film semiconductor structure disposed over the third gate in the first axis direction, the N-type thin-film semiconductor structure comprising a third source/drain region, a fourth source/drain region, and a second channel region between the third and fourth source/drain regions; and
a fourth gate disposed over the N-type thin-film semiconductor structure in the first axis direction opposite to the third gate; and
at least one metal contact electrically coupling the second source/drain region of the at least one PFET and the third source/drain region of the at least one NFET.

### Claim 2 (depends on 1)

The CMOS circuit of claim 1, wherein:
a PFET of the at least one PFET further comprises:
a first metal contact disposed on the first source/drain region; and
a second metal contact disposed on the second source/drain region; and
an NFET of the at least one NFET further comprises:
a third metal contact disposed on the third source/drain region; and
a fourth metal contact disposed on the fourth source/drain region;
wherein the at least one metal contact coupling the second source/drain region and the third source/drain region comprises the second metal contact and the third metal contact.

### Claim 3 (depends on 2)

The CMOS circuit of claim 2, wherein:
the PFET of the at least one PFET further comprises:
a first dielectric layer extending between one of at least one side surface of the first metal contact and a first side surface of the second gate, between the P-type thin-film semiconductor structure and a bottom surface of the second gate, and between one of at least one side surface of the second metal contact and a second side surface of the second gate opposite to the first side surface of the second gate; and
the NFET of the at least one NFET further comprises:
a second dielectric layer extending between one of at least one side surface of the third metal contact and a first side surface of the fourth gate, between the N-type thin-film semiconductor structure and a bottom surface of the fourth gate, and between one of at least one side surface of the fourth metal contact and a second side surface of the fourth gate opposite to the first side surface of the fourth gate.

### Claim 4 (depends on 1)

The CMOS circuit of claim 1, wherein:
the first gate and the second gate are configured to induce inversion channel layers in a bottom surface and a top surface, respectively, of the first channel region; and
the third gate and the fourth gate are configured to induce inversion channel layers in a bottom surface and a top surface, respectively, of the second channel region.

### Claim 5 (depends on 1)

The CMOS circuit of claim 1, further comprising:
a signal input coupled to the first gate and the third gate; and
a signal output coupled to the at least one metal contact.

### Claim 6 (depends on 1)

The CMOS circuit of claim 1, wherein the flexible substrate has a flexibility to bend in a range of approximately 0 to 90 degrees.

### Claim 7 (depends on 1)

The CMOS circuit of claim 1, wherein the second gate is directly coupled to the first gate, and the fourth gate is directly coupled to the third gate.

### Claim 8 (depends on 1)

The CMOS circuit of claim 1, wherein:
the P-type thin-film semiconductor structure comprises Ge2Sb2Te5 (Germanium Antimony Tellurium) (GST); and
the N-type thin-film semiconductor structure comprises InGaZnO4 (Indium Gallium Zinc Oxide) (IGZO).

### Claim 9 (depends on 1)

The CMOS circuit of claim 1, integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

### Claim 10

A method of fabricating a complementary metal-oxide semiconductor (CMOS) circuit on a flexible substrate, comprising:
forming a first gate and a second gate on a surface of the flexible substrate;
forming a P-type semiconductor structure over the first gate in a first axis direction;
forming an N-type semiconductor structure over the second gate in the first axis direction;
forming first and second P-type Field-Effect Transistor (FET) (PFET) source/drain regions in first and second end portions, respectively, of the P-type semiconductor structure;
forming third and fourth N-type FET (NFET) source/drain regions in first and second end portions, respectively, of the N-type semiconductor structure;
forming a first metal contact on the second PFET source/drain region and a second metal contact on the third NFET source/drain region, electrically coupling the second PFET source/drain region and the third NFET source/drain region through the first metal contact and the second metal contact;
forming a third gate over the P-type semiconductor structure opposite to the first gate in the first axis direction; and
forming a fourth gate over the N-type semiconductor structure opposite to the second gate in the first axis direction.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
forming a third metal contact on the first PFET source/drain region; and
forming a fourth metal contact on the fourth NFET source/drain region.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
forming a dielectric on the first, second, third, and fourth metal contacts, the P-type semiconductor structure, and the N-type semiconductor structure, the dielectric disposed between a side surface of the first metal contact and a first side surface of the third gate, between a side surface of the third metal contact and a second side surface of the third gate, between a side surface of the second metal contact and a first side surface of the fourth gate, and between a side surface of the fourth metal contact and a second side surface of the fourth gate.

### Claim 13 (depends on 10)

The method of claim 10, wherein:
forming the P-type semiconductor structure over the first gate comprises forming the first and second end portions of the P-type semiconductor structure to be adjacent to first and second side surfaces, respectively, of the first gate, and
forming the N-type semiconductor structure over the second gate comprises forming the first and second end portions of the N-type semiconductor structure to be adjacent to first and second side surfaces, respectively, of the fourth gate.

### Claim 14 (depends on 10)

The method of claim 10, further comprising:
forming an electrode on top surfaces of the first and second metal contacts.

### Claim 15 (depends on 10)

The method of claim 10, wherein:
the N-type semiconductor structure comprises InGaZnO4 (Indium Gallium Zinc Oxide) (IGZO); and
the P-type semiconductor structure comprises Ge2Sb2Te5 (Germanium Antimony Tellurium) (GST).