# US 10,483,283 B2 · Flash memory device and manufacture thereof

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- Number: US 10,483,283 B2
- Document ID: US10483283B2
- Status: Granted
- Kind: B2
- Application number: 16/379,422
- Filed: 2019-04-09
- Published: 2019-08-01
- Granted: 2019-11-19
- Earliest claimed: 2016-10-31
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Shan Rong Li; Min-hwa Chi; Sheng Fen Chiu
- Web page: https://patentgrep.com/patent/US10483283B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 30/689: {Vertical floating-gate IGFETs}
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 62/40: Crystalline structures
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/64: Electrodes comprising a Schottky barrier to a semiconductor
- H10D 64/647: {Schottky drain or source electrodes for IGFETs}
- H10B 43/10: characterised by the top-view layout
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A flash memory device and its manufacturing method are presented. The flash memory device includes a substrate; a memory unit on the substrate, comprising a channel structure, wherein the channel structure comprises, sequentially from inner to outer of the channel structure, a channel layer comprising a first component substantially perpendicular to an upper surface of the substrate and a second component on the first component, a tunnel insulation layer wrapped around the channel layer, a charge capture layer wrapped around the tunnel insulation layer, and a blocking layer wrapped around the charge capture layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure with a topmost gate structure wrapped around the second component; and a channel contact component connecting to, and forming a Schottky contact with, the second component of the channel layer. This device reduces the leakage current.

## Claims

### Claim 1

A method for manufacturing a flash memory device, comprising:
providing a substrate;
forming a plurality of sacrificial layers and a plurality of interval insulation layers on the substrate, with the sacrificial layers and the interval insulation layers stacking over each other alternately;
forming a through-hole by etching the sacrificial layers and the interval insulation layers until an upper surface of the substrate is exposed;
forming a channel structure in the through-hole, wherein the channel structure comprises, sequentially from inner to outer of the channel structure, a channel layer, a tunnel insulation layer wrapped around the channel layer, a charge capture layer wrapped around the tunnel insulation layer, and a blocking layer wrapped around the charge capture layer, wherein the channel layer comprises a first component substantially perpendicular to the upper surface of the substrate and a second component on the first component;
forming a plurality of interval cavities by removing the sacrificial layers;
forming a plurality of gate structures in the interval cavities, with a topmost gate structure wrapped around the second component of the channel layer; and
forming a channel contact component contacting the second component of the channel layer, wherein the channel contact component and the second component of the channel layer form a Schottky contact.

### Claim 2 (depends on 1)

The method of claim 1, wherein the conduction types of the first component and the second component of the channel layer are opposite to each other.

### Claim 3 (depends on 1)

The method of claim 1, wherein the conduction types of the first component and the second component of the channel layer are N-type and P-type, respectively, or P-type and N-type, respectively.

### Claim 4 (depends on 1)

The method of claim 1, wherein the channel layer is made of polycrystalline silicon, the tunnel insulation layer is made of silicon-based oxide, the charge capture layer is made of silicon-based nitride, and the blocking layer is made of silicon-based oxide.

### Claim 5 (depends on 1)

The method of claim 1, wherein the channel contact component comprises:
a top interface layer contacting the second component of the channel layer; and
a metal filling layer on the top interface layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the conduction type of the second component of the channel layer is P-type and the top interface layer is a P-type work function interface layer, or, the conduction type of the second component of the channel layer is N-type and the top interface layer is an N-type work function interface layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the channel layer further comprises a third component underneath the first component, with a bottommost gate structure wrapped around the third component.

### Claim 8 (depends on 1)

The method of claim 1, wherein the channel structure further comprises a channel kernel being wrapped by the channel layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein forming a channel structure in the through-hole comprises:
forming the blocking layer on a side surface of the through-hole;
forming the charge capture layer on a side surface of the blocking layer;
forming the tunnel insulation layer on a side surface of the charge capture layer;
forming the channel layer on a side surface of the tunnel insulation layer and the bottom of the through-hole, wherein the channel layer comprises the first component substantially perpendicular to the upper surface of the substrate and a third component underneath the first component;
forming a channel kernel partially filling the through-hole on the channel layer, wherein an upper surface of the channel kernel is lower than an upper surface of the topmost sacrificial layer;
removing a portion of the channel layer higher than the channel kernel; and
forming the second component of the channel layer connecting to the first component of the channel layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein forming a channel structure in the through-hole further comprises:
forming a top insulation layer covering the second component of the channel layer after the second component of the channel layer is formed,
and wherein forming a channel contact component comprises:
forming an opening exposing the second component of the channel layer by etching the top insulation layer; and
forming the channel contact component in the opening.

### Claim 11 (depends on 1)

The method of claim 1, further comprises:
forming a bottom interface layer on a portion of the substrate before the sacrificial layers and the interval insulation layers are formed on the substrate, wherein the bottom interface layer comprises a work function regulation layer, and the sacrificial layers and the interval insulation layers are formed on the bottom interface layer,
wherein when forming the through-hole, the through-hole exposes an upper surface of the bottom interface layer,
and wherein when forming the channel structure, the channel layer contacts the bottom interface layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein the conduction type of the first component of the channel layer is N-type and the bottom interface layer is an N-type work function interface layer, or, the conduction type of the first component of the channel layer is P-type and the bottom interface layer is a P-type work function interface layer.

### Claim 13 (depends on 11)

The method of claim 11, further comprises:
forming a channel groove exposing the upper surface of the bottom interface layer by etching the sacrificial layers and the interval insulation layers after the channel structure is formed but before the sacrificial layers are removed;
forming a sidewall interval layer on a side surface of the channel groove after the gate structures are formed but before the channel contact component is formed; and
forming a metal contact component contacting the bottom interface layer in the channel groove after the sidewall interval layer is formed.