# US 10,483,281 B2 · Semiconductor memory device

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- Number: US 10,483,281 B2
- Document ID: US10483281B2
- Status: Granted
- Kind: B2
- Application number: 16/189,625
- Filed: 2018-11-13
- Published: 2019-03-14
- Granted: 2019-11-19
- Earliest claimed: 2016-11-04
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Yung Jun Kim; Suk Goo Kim
- Web page: https://patentgrep.com/patent/US10483281B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- H10B 43/10: characterised by the top-view layout
- H10B 43/30: characterised by the memory core region
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/06: Auxiliary circuits, e.g. for writing into memory
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor memory device includes a cell array region formed on a substrate, a word line contact region, and a page buffer region coupled to the cell array region through bit lines, wherein at least one of the bit lines has a curved structure toward the word line contact region. According to an embodiment, a misalignment between a cell plug and a contact plug caused by a natural cell plug bending phenomenon may be reduced to improve operational reliability of a semiconductor memory device.

## Claims

### Claim 1

A method of manufacturing a semiconductor memory device comprising:
forming bit lines on a substrate, wherein the substrate includes a cell array region, a word line contact region and a page buffer region;
wherein the page buffer region is coupled to the cell array region through bit lines,
wherein the bit lines include a first bit line and a second bit line, and
wherein the second bit line has a curved structure toward the word line contact region and a curvedness of the second bit line is greater than a curvedness of the first bit line.

### Claim 2 (depends on 1)

The method of claim 1, wherein the bit lines have a curved structure and curvedness of the bit lines increases toward the word line contact region.

### Claim 3 (depends on 1)

The method of claim 1, wherein curvedness of the bit lines increases in a direction from a center toward at least one bit line located over one edge and/or the other edge of the cell array region.

### Claim 4 (depends on 1)

The method of claim 1,
wherein the word line contact region is located on at least one of a first side of the cell array region and a second side of the cell array region opposite to the first side, and
wherein the page buffer region is located at a third side coupling the first and second sides of the cell array region.

### Claim 5 (depends on 1)

The method of claim 1, wherein the bit lines extend over the cell array region and the page buffer region.

### Claim 6 (depends on 1)

The method of claim 1, wherein each of the bit lines includes a first portion placed on the cell array region, a second portion placed on the page buffer region, and a third portion placed between the cell array region and the page buffer region, the third portion connecting the first and second portions of each bit line.

### Claim 7 (depends on 6)

The method of claim 6, wherein two or more of third portions of the bit lines have different shapes from each other.

### Claim 8 (depends on 6)

The method of claim 6, wherein two or more of third portions of the bit lines have slopes increasing in a direction from a third portion located at a center toward at least one of a third portion located at one edge and a third portion located at the other edge.

### Claim 9 (depends on 6)

The method of claim 6, wherein at least one of first portions of the bit lines has a greater line width than at least one of second portions thereof.

### Claim 10 (depends on 6)

The method of claim 6, wherein a line width of at least one of third portions increases towards the word line contact region.

### Claim 11 (depends on 6)

The method of claim 6, wherein at least one of distances between first portions is the same as at least one of distances between second portions.

### Claim 12 (depends on 1)

The method of claim 1, further comprising:
forming a stepwise stacked structure in the word line contact region,
wherein the stepwise stacked structure includes interlayer insulating layers and conductive layers alternately stacked on the substrate.

### Claim 13 (depends on 1)

The method of claim 1, wherein the forming of the bit lines comprises:
forming an insulating layer over the substrate;
forming a plurality of mask patterns on the insulating layer at the cell array region and the page buffer region;
forming a plurality of spacer pairs on respective sidewalls of the mask patterns;
removing the mask patterns;
forming trenches in the insulating layer by etching the insulating layer using the spacer pairs as an etch barrier; and
forming the bit lines in the trenches, respectively.

### Claim 14 (depends on 13)

The method of claim 13, wherein at least one of the mask patterns has a greater width in the cell array region than in the page buffer region, and
wherein at least one of the spacer pairs has a greater distance in the cell array region than in the page buffer region.

### Claim 15

A method of manufacturing a semiconductor memory device comprising:
forming a stacked structure on a substrate, wherein the stacked structure includes word lines stacked on a cell array region a substrate and cell plugs, wherein the substrate includes the cell array region, a word line contact region and a page buffer region;
forming first contact plugs coupled to the cell plugs in the cell array region;
forming second contact plugs coupled to transistors in the page buffer region; and
forming bit lines coupling the first contact plugs and the second plugs so that the page buffer region is coupled to the cell array region through the bit lines,
wherein one of the first contact plugs is shifted to the word line contact region with respect to a corresponding second contact plug and a distance by which the one of the first contact plugs is shifted with respect to the corresponding second contact plug is greater than a distance by which another first contact plug is shifted with respect to a corresponding second contact plug.

### Claim 16 (depends on 15)

The method of claim 15, wherein the distance by which the one of the first contact plugs is shifted increases toward the word line contact region.

### Claim 17

A method of manufacturing a semiconductor memory device comprising:
forming a stacked structure on a substrate, wherein the stacked structure includes cell plugs extending from a substrate and conductive layers surrounding the cell plugs and extending in a first direction; and
forming bit lines coupled to the cell plugs and extending in a second direction crossing the first direction,
wherein the bit lines include a first bit line and a second bit line adjacent to each other in the first direction, and
wherein the second bit line has a curved structure in the first direction and a curvedness of the second bit line is greater than a curvedness of the first bit line.

### Claim 18 (depends on 17)

The method of claim 17, wherein curvedness of the bit lines increases in the first direction.

### Claim 19 (depends on 17)

The method of claim 17, wherein the conductive layers extend in the first direction to form a stepwise structure.

### Claim 20

A method of manufacturing a semiconductor memory device comprising:
forming an insulating layer over a substrate, wherein the substrate includes a cell array region and a page buffer region;
forming a plurality of mask patterns over the insulating layer at the cell array region and the page buffer region;
forming a plurality of spacer pairs on respective sidewalls of the mask patterns;
removing the mask patterns;
forming trenches in the insulating layer by etching the insulating layer using the spacer pairs as an etch barrier; and
forming the bit lines in the trenches, respectively,
wherein at least one of the mask patterns has a greater width in the cell array region than in the page buffer region,
wherein at least one of the spacer pairs has a greater distance in the cell array region than in the page buffer region, and
wherein the bit lines include a first bit line and a second bit line, the second bit line has a curved structure and a curvedness of the second bit line is greater than a curvedness of the first bit line.