# US 10,483,279 B2 · Method of manufacturing a semiconductor device

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- Number: US 10,483,279 B2
- Document ID: US10483279B2
- Status: Granted
- Kind: B2
- Application number: 15/753,376
- Filed: 2015-11-23
- Published: 2018-08-23
- Granted: 2019-11-19
- Earliest claimed: 2015-08-20
- Assignees: Institute of Microelectronics, Chinese Academy of Sciences
- Applicants: Institute of Microelectronics, Chinese Academy of Sciences
- Inventors: Tianchun Ye
- Web page: https://patentgrep.com/patent/US10483279B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 64/037: {comprising charge-trapping insulators}
- H10P 14/3454: {Amorphous}
- H10P 50/642: {Chemical etching}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10P 14/3406: {Carbon, e.g. diamond-like carbon}
- H10P 14/3408: {Silicon carbide}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3414: {being group IIIA-VIA materials}
- H10P 14/3424: {being Group IIB-VIA materials}
- H10P 14/3802: {Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a semiconductor device, comprising the steps of: forming a gate dielectric layer and a first amorphous channel layer on a substrate; thinning the first amorphous channel layer; etching the first amorphous channel layer and the gate dielectric layer until the substrate is exposed; forming a second amorphous channel layer on the first amorphous channel layer and the substrate; annealing such that the first amorphous channel layer and the second amorphous channel layer are converted into a polycrystalline channel layer; and thinning the polycrystalline channel layer. According to the method of manufacturing semiconductor device of the present invention, the grain size of the polycrystalline thin film is increased by depositing a thick amorphous film and then annealing and thinning it. An additional protective layer is used to avoid etching damage on the sidewalls, effectively reducing the interface state and damage defects of the polycrystalline channel layer, thereby enhancing the reliability of the device.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising the steps of:
forming a gate dielectric layer and a first amorphous channel layer on a substrate;
thinning the first amorphous channel layer;
etching the first amorphous channel layer and the gate dielectric layer until the substrate is exposed;
forming a second amorphous channel layer on the first amorphous channel layer and the substrate;
annealing such that the first amorphous channel layer and the second amorphous channel layer are converted into a polycrystalline channel layer;
thinning the polycrystalline channel layer.

### Claim 2 (depends on 1)

The method according to claim 1, wherein, the gate dielectric layer includes a plurality of sub-layers selected from a tunneling layer, a storage layer and a barrier layer.

### Claim 3 (depends on 1)

The method according to claim 1, wherein, the first amorphous channel layer is selected from amorphous Si or amorphous Ge.

### Claim 4 (depends on 1)

The method according to claim 1, wherein, the second amorphous channel layer is selected from amorphous Ge, amorphous SiGe, amorphous SiC, amorphous SiGeC, amorphous C, group III-V or group II-VI amorphous compound semiconductors, and combinations thereof.

### Claim 5 (depends on 1)

The method according to claim 1, wherein, the second amorphous channel layer comprises a dopant, and the annealing activates the said dopant.

### Claim 6 (depends on 1)

The method according to claim 1, wherein, after thinning the first amorphous channel layer and before etching the first amorphous channel layer, the method further comprises forming a protective layer on the first amorphous channel layer, the protective layer is a single layer or multi-layer structure.

### Claim 7 (depends on 6)

The method according to claim 6, wherein, after etching to expose the substrate, and before forming the second amorphous channel layer, the method further includes removing the protective layer by etching.

### Claim 8 (depends on 1)

The method according to claim 1, wherein, the step of forming the gate dielectric layer and the first amorphous channel layer on the substrate comprises forming a dummy gate stack on the substrate, etching the dummy gate stack to form a plurality of channel trenches perpendicular to the substrate, sequentially depositing a gate dielectric layer and a first amorphous channel layer in each channel trench.

### Claim 9 (depends on 8)

The method according to claim 8, wherein, after thinning the polycrystalline channel layer, the method further includes forming a plurality of source and drain regions on the upper and lower ends of the polycrystalline channel layer, removing the dummy gate stack, and forming a gate conductive layer on the sidewalls of the gate dielectric layer.

### Claim 10 (depends on 1)

The method according to claim 1, wherein, the temperature of annealing is 300˜850° C., the annealing time is from 1 minute to 10 hours.