# US 10,483,275 B2 · Semiconductor device and method of manufacturing the same

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- Number: US 10,483,275 B2
- Document ID: US10483275B2
- Status: Granted
- Kind: B2
- Application number: 16/243,319
- Filed: 2019-01-09
- Published: 2019-05-16
- Granted: 2019-11-19
- Earliest claimed: 2016-07-08
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Shibun Tsuda
- Web page: https://patentgrep.com/patent/US10483275B2

## CPC

- H10B 43/30: characterised by the memory core region
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate}
- H10D 30/697: {having trapping at multiple separated sites, e.g. multi-particles trapping sites}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83125: {the IGFETs characterised by having shared source or drain regions}
- H10D 84/834: {comprising FinFETs}
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a semiconductor device includes forming a first insulating film having a first thickness over a main surface of a semiconductor substrate and then forming a second insulating film having a second thickness larger than the first thickness over the first insulating film, sequentially processing the second insulating film, the first insulating film, and the semiconductor substrate to form a plurality of trenches and to form a plurality of projecting portions which include portions of the semiconductor substrate extending in a first direction along the main surface of the semiconductor substrate and are spaced apart from each other in a second direction orthogonal to the first direction along the main surface of the semiconductor substrate, and depositing a third insulating film over the main surface of the semiconductor substrate such that the third insulating film is embedded in the trenches.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
(a) forming a first insulating film having a first thickness over a main surface of a semiconductor substrate and then forming a second insulating film having a second thickness larger than the first thickness over the first insulating film;
(b) sequentially processing the second insulating film, the first insulating film, and the semiconductor substrate to form a plurality of trenches and to form a plurality of projecting portions which include portions of the semiconductor substrate extending in a first direction along the main surface of the semiconductor substrate and are spaced apart from each other in a second direction orthogonal to the first direction along the main surface of the semiconductor substrate;
(c) depositing a third insulating film over the main surface of the semiconductor substrate such that the third insulating film is embedded in the trenches;
(d) planarizing an upper surface of the third insulating film and an upper surface of the second insulating film;
(e) removing the second insulating film;
(f) performing isotropic dry etching to remove the first insulating film, expose respective upper surfaces of the projecting portions, recess an upper surface and a side surface of the third insulating film, and expose respective side walls of the projecting portions from the upper surface of the third insulating film;
(g) forming a first gate electrode extending in the second direction such that a fourth insulating film is interposed between the first gate electrode and each of the respective upper surfaces and side walls of the projecting portions which are exposed from the upper surface of the third insulating film; and
(h) forming a second gate electrode extending in the second direction such that a fifth insulating film including a trapping insulating film is interposed between the second gate electrode and each of the respective upper surfaces and side walls of the projecting portions which are exposed from the upper surface of the third insulating film and one of side walls of the first gate electrode,
wherein, between the projecting portions adjacent to each other in the second direction, a portion of the upper surface of the third insulating film is higher in level than a first surface obtained by connecting a position of the upper surface of the third insulating film which is in contact with the side wall of one of the projecting portions to a position of the upper surface of the third insulating film which is in contact with the side wall of other projecting portion.

### Claim 2 (depends on 1)

The method of manufacturing the semiconductor device according to claim 1, wherein, in the (a), the second insulating film having a multi-layer structure including a first silicon nitride film, a silicon dioxide film, and a second silicon nitride film is formed, and
wherein the (e) includes:
(e1) removing the second silicon nitride film;
(e2) performing isotropic dry etching to remove the silicon dioxide film and recess the upper surface and side surface of the third insulating film; and
(e3) removing the first silicon nitride film.

### Claim 3 (depends on 1)

The method of manufacturing the semiconductor device according to claim 1, further including, between the (e) and the (f):
(i) performing etching to recess the upper surface of the third insulating film.

### Claim 4 (depends on 1)

The method of manufacturing the semiconductor device according to claim 1, wherein, when a width of the first surface in the second direction is W and a distance from the first surface to a highest position of the upper surface of the third insulating film is H, H/W is in a range from 0.2 to 0.5.

### Claim 5 (depends on 1)

The method of manufacturing the semiconductor device according to claim 1, wherein a distance from the first surface to a highest position of the upper surface of the third insulating film is in a range from 20 nm to 30 nm.