# US 10,483,272 B2 · Electronic device and method for fabricating the same

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- Number: US 10,483,272 B2
- Document ID: US10483272B2
- Status: Granted
- Kind: B2
- Application number: 16/242,320
- Filed: 2019-01-08
- Published: 2019-05-09
- Granted: 2019-11-19
- Earliest claimed: 2015-11-30
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Kwang-Seok Oh
- Web page: https://patentgrep.com/patent/US10483272B2

## CPC

- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- G06F 12/0893: Caches characterised by their organisation or structure
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 99/00: Subject matter not provided for in other groups of this subclass
- H10D 1/00: Resistors, capacitors or inductors
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- G06F 2212/603: of operating mode, e.g. cache mode or local memory mode
- H10B: ELECTRONIC MEMORY DEVICES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a first channel layer formed over a substrate and extending in a vertical direction; a first stacked structure comprising a plurality of first interlayer dielectric layers and a plurality of first gate electrode layers which are alternately stacked along the first channel layer; a first memory layer interposed between the first channel layer and the first gate electrode layers; a second channel layer formed over the first channel layer and extending in the vertical direction; a second stacked structure comprising a plurality of second interlayer dielectric layers and a plurality of second gate electrode layers which are alternately stacked along the second channel layer; a second memory layer interposed between the second channel layer and the second gate electrode layers; a first channel connection pattern formed between the first channel layer and the second channel layer and coupling the first and the second channel layers to each other; and a first etch stop pattern formed between the first and second stacked structures and at substantially the same level as the first channel connection pattern, wherein the first etch stop pattern includes the same material as the first channel connection pattern and is isolated from the first channel connection pattern.

## Claims

### Claim 1

A method for fabricating an electronic device including a semiconductor memory, comprising:
forming a first stacked structure over a substrate, the first stacked structure including a plurality of first interlayer dielectric layers and first material layers which are alternately stacked over each other;
forming a first channel hole by selectively etching the first stacked structure;
forming a first channel layer in the first channel hole;
forming a channel connection pattern and an etch stop pattern over the first stacked structure, wherein the channel connection pattern overlaps the first channel hole and, wherein the etch stop pattern is formed of the same material as the channel connection pattern, is isolated from the channel connection pattern, and is formed at substantially the same level as the channel connection pattern;
forming a second stacked structure over the channel connection pattern and the etch stop pattern, the second stacked structure including a plurality of second interlayer dielectric layers and second material layers which are alternately stacked over each other;
forming a second channel hole to expose the channel connection pattern by selectively etching the second stacked structure;
forming a second channel layer in the second channel hole;
forming an initial slit by etching the second stacked structure to expose the etch stop pattern; and
forming a final slit by etching the exposed etch stop pattern and the first stacked structure located under the exposed etch stop pattern.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
providing an insulating material between the channel connection pattern and the etch stop pattern.

### Claim 3 (depends on 1)

The method of claim 1, wherein the channel connection pattern has a larger width than a top surface of the first channel hole and a bottom surface of the second channel hole.

### Claim 4 (depends on 1)

The method of claim 1, wherein the etch stop pattern has a width greater than the slit.

### Claim 5 (depends on 1)

The method of claim 1, wherein the forming of the first channel layer comprises:
forming a memory material and a channel material in the first channel hole; and
etching the memory material and the channel material through a blanket etch process until a bottom surface of the first channel hole is exposed.

### Claim 6 (depends on 1)

The method of claim 1, wherein the forming of the second channel layer comprises:
forming a memory material and a channel material in the second channel hole; and
etching the memory material and the channel material through a blanket etch process until a bottom surface of the second channel hole is exposed.

### Claim 7 (depends on 5)

The method of claim 5, further comprising:
forming an epitaxial layer over the bottom surface of the first channel hole after the etching of the memory material and the channel material.

### Claim 8 (depends on 6)

The method of claim 6, further comprising:
forming an epitaxial layer over the bottom surface of the second channel hole after the etching of the memory material and the channel material.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
forming a first memory layer over a sidewall of the first channel hole,
wherein the first channel layer is formed over the first memory layer.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
forming a second memory layer over a sidewall of the second channel hole,
wherein the second channel layer is formed over the second memory layer.

### Claim 11 (depends on 1)

The method of claim 1, further comprising:
after the forming of the final slit, removing the first and the second material layers exposed through the final slit to form first spaces and second spaces, respectively; and
filling first and second conductive materials in the first and the second spaces, respectively.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
forming a first memory layer along inner walls of the first spaces; and
forming a second memory layer along inner walls of the second spaces,
wherein the first conductive material is formed over the first memory layer, and
wherein the second conductive material is formed over the second memory layer.

### Claim 13 (depends on 1)

The method of claim 1, further comprising:
forming a gate electrode layer in the substrate;
forming a sacrificial layer in the gate electrode layer so that the gate electrode layer surrounds a sidewall and a bottom surface of the sacrificial layer;
forming a third channel hole by selectively etching the first stacked structure, wherein the third channel layer is arranged in parallel to the first channel hole and at substantially the same level, wherein the first and the third channel holes expose the sacrificial layer;
removing the sacrificial layer through the first and the third channel holes to form a trench in the gate electrode layer; and
forming a memory layer over inner surfaces of the first channel hole, the third channel hole, and the trench.

### Claim 14 (depends on 1)

The method of claim 1, further comprising:
forming a conductive layer in the substrate; and
forming a third channel hole by selectively etching the first stacked structure,
wherein the third channel layer is arranged in parallel to the first channel hole and at substantially the same level, and wherein the first and the third channel holes expose the conductive layer.