# US 10,483,271 B2 · Non-volatile memory structure and manufacturing method thereof

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- Number: US 10,483,271 B2
- Document ID: US10483271B2
- Status: Granted
- Kind: B2
- Application number: 15/911,176
- Filed: 2018-03-05
- Published: 2019-07-04
- Granted: 2019-11-19
- Earliest claimed: 2018-01-04
- Assignees: Powerchip Semiconductor Manufacturing Corporation
- Applicants: Powerchip Semiconductor Manufacturing Corporation
- Inventors: Zih-Song Wang
- Web page: https://patentgrep.com/patent/US10483271B2

## CPC

- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/10: characterised by the top-view layout
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10W 10/051: {of isolation region based on field-effect}
- H10W 10/50: Isolation regions based on field-effect
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A non-volatile memory structure including memory cells, at least one isolation layer, and at least one shield electrode is provided. The memory cells are disposed on a substrate. The isolation layer is located between the memory cells. The shield electrode is disposed on the isolation layer and electrically connected to a source line.

## Claims

### Claim 1

A non-volatile memory structure, comprising:
memory cells disposed on a substrate;
at least one isolation layer located between the memory cells; and
at least one shield electrode disposed on the at least one isolation layer and electrically connected to a source line wherein the non-volatile memory structure is a vertical non-volatile memory structure, and the vertical non-volatile memory structure comprises:
a stacked structure disposed on the substrate and comprising the at least one shield electrode, gate structures, and the at least one isolation layer, wherein the at least one shield electrode and the gate structures are alternately stacked, and the at least one isolation layer is located between the at least one shield electrode and the gate structures; a channel layer disposed on a sidewall at a side of the stacked structure; and a charge storage structure layer disposed between the stacked structure and the channel layer.

### Claim 2 (depends on 1)

The non-volatile memory structure of claim 1, wherein the non-volatile memory structure is a planar non-volatile memory structure.

### Claim 3 (depends on 2)

The non-volatile memory structure of claim 2, wherein each of the memory cells comprises:
a charge storage layer disposed on the substrate;
a conductor layer disposed on the charge storage layer;
a first dielectric layer disposed between the charge storage layer and the substrate; and
a second dielectric layer disposed between the conductor layer and the charge storage layer.

### Claim 4 (depends on 3)

The non-volatile memory structure of claim 3, wherein the conductor layer is further disposed between the charge storage layers, and the second dielectric layer is further disposed between the conductor layer and the at least one shield electrode.

### Claim 5 (depends on 2)

The non-volatile memory structure of claim 2, wherein the at least one isolation layer is disposed in the substrate between the memory cells and disposed between the at least one shield electrode and the substrate.

### Claim 6 (depends on 5)

The non-volatile memory structure of claim 5, wherein the at least one isolation layer comprises:
at least one isolation structure disposed in the substrate between the memory cells; and
at least one liner layer disposed between the at least one isolation structure and the substrate and disposed between the at least one shield electrode and the substrate.

### Claim 7 (depends on 1)

The non-volatile memory structure of claim 1, wherein the memory cells comprise the gate structures and a portion of the charge storage structure layer located at a side of the gate structures.

### Claim 8 (depends on 1)

The non-volatile memory structure of claim 1, wherein the source line is disposed on a sidewall at another side of the stacked structure and connected to the substrate, and the at least one isolation layer is further located between the source line and the gate structures.

### Claim 9 (depends on 1)

The non-volatile memory structure of claim 1, wherein each of the gate structures comprises a metal gate layer and a barrier layer, and the barrier layer is located between the metal gate layer and the charge storage structure layer.