# US 10,483,270 B2 · Integrated assemblies and methods of forming integrated assemblies

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,483,270 B2
- Document ID: US10483270B2
- Status: Granted
- Kind: B2
- Application number: 16/270,526
- Filed: 2019-02-07
- Published: 2019-07-04
- Granted: 2019-11-19
- Earliest claimed: 2015-11-23
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Justin B. Dorhout; Kunal R. Parekh; Martin C. Roberts; Mohd Kamran Akhtar; Chet E. Carter; David Daycock
- Web page: https://patentgrep.com/patent/US10483270B2

## CPC

- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 20/383: {Channel doping programmed}
- H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 41/23: with source and drain on different levels, e.g. with sloping channels
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10P 32/30: Diffusion for doping of conductive or resistive layers
- H10P 32/302: {Doping polycrystalline silicon or amorphous silicon layers}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 50/73: {using masks for insulating materials}
- H10P 72/0418: {for etching}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10B 43/35: with cell select transistors, e.g. NAND
- H10W 20/0765: {the thin functional dielectric layers being temporary, e.g. sacrificial layers}
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

## Claims

### Claim 1

An integrated assembly, comprising:
a first channel structure extending substantially vertically;
a second channel structure extending substantially vertically; each of the first and the second semiconductor channel structures having a first doped channel region interfacing a second doped channel region at a boundary region, the first doped channel regions being differently doped relative to the second doped channel regions; and
a gating structure extending between the first channel structure and the second channel structure and having a first gating region extending along the first channel structure, a second gating region extending along the second channel structure, and an interconnecting region extending laterally between the first and second gating regions, the interconnecting region being vertically narrower than first and second the gating regions.

### Claim 2

The integrated assembly of claim wherein all of the first and second doped channel regions are doped to have the same majority carriers.

### Claim 3 (depends on 2)

The integrated assembly of claim 2 wherein said same majority carriers are majority carriers are n-type.

### Claim 4 (depends on 2)

The integrated assembly of claim 2 wherein said same majority carriers are p-type.

### Claim 5 (depends on 1)

The integrated assembly of claim 1 wherein a first part of the gating structure and the first channel structure are incorporated into a select device electrically coupled in series with a plurality of memory cells.

### Claim 6 (depends on 5)

The integrated assembly of claim 5 wherein the plurality of memory cells are vertically-stacked over the select device.

### Claim 7 (depends on 1)

The integrated assembly of claim 1 wherein the first and second channel structures are supported by a semiconductor base having a substantially horizontal primary surface, and wherein the first and second channel structures extend primarily substantially orthogonally relative to the substantially horizontal primary surface.

### Claim 8 (depends on 1)

The integrated assembly of claim 1 wherein the gating structure extends within a stack of alternating first and second insulating materials; a bottom surfaces of the gating regions being along a lower tier of the first insulating, material; a bottom surface of the interconnecting region being along a higher tier of the first insulating material; and an intermediate tier of the second insulating material being between the lower and higher tiers of the first insulating material and being directly against side surfaces of the gating regions.