# US 10,483,266 B2 · Flexible merge scheme for source/drain epitaxy regions

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- Number: US 10,483,266 B2
- Document ID: US10483266B2
- Status: Granted
- Kind: B2
- Application number: 15/492,142
- Filed: 2017-04-20
- Published: 2018-10-25
- Granted: 2019-11-19
- Earliest claimed: 2017-04-20
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Kai-Hsuan Lee; Chia-Ta Yu; Cheng-Yu Yang; Sheng-Chen Wang; Sai-Hooi Yeong; Feng-Cheng Yang; Yen-Ming Chen
- Web page: https://patentgrep.com/patent/US10483266B2

## CPC

- H10B 10/12: {comprising a MOSFET load element}
- H10B 10/18: {Peripheral circuit regions}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10P 50/283: {by chemical means}
- H10P 50/642: {Chemical etching}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/204: {of organic photoresist masks}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

## Claims

### Claim 1

A method comprising:
forming a first gate stack extending on top surfaces and sidewalls of first semiconductor fins, wherein the first semiconductor fins are parallel to, and are neighboring, each other;
forming a second gate stack extending on top surfaces and sidewalls of second semiconductor fins, wherein the second semiconductor fins are parallel to, and are neighboring, each other;
forming a dielectric layer, wherein the dielectric layer comprises a first portion extending on the first gate stack and the first semiconductor fins, and a second portion extending on the second gate stack and the second semiconductor fins;
in a first etching process, etching the first portion of the dielectric layer to form first fin spacers on sidewalls of the first semiconductor fins, wherein the first fin spacers have a first height;
in a second etching process, etching the second portion of the dielectric layer to form second fin spacers on sidewalls of the second semiconductor fins, wherein the second fin spacers have a second height greater than the first height;
recessing the first semiconductor fins to form first recesses between the first fin spacers;
recessing the second semiconductor fins to form second recesses between the second fin spacers; and
simultaneously growing first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses, wherein the first epitaxy semiconductor regions grown from neighboring ones of the first recesses merge with each other, and the second epitaxy semiconductor regions grown from neighboring ones of the second recesses are separate from each other.

### Claim 2 (depends on 1)

The method of claim 1, wherein the neighboring first semiconductor fins have a first distance, and neighboring second semiconductor fins have a second distance greater than the first distance.

### Claim 3 (depends on 1)

The method of claim 1 further comprising:
forming a mask layer over the dielectric layer;
forming a first photo resist over the second gate stack and the second semiconductor fins;
etching a first portion of the mask layer directly over the first gate stack and the first semiconductor fins; and
etching a first portion of the dielectric layer covered by the etched first portion of the mask layer to form the first fin spacers; and
removing the first photo resist after the first recesses are formed.

### Claim 4 (depends on 3)

The method of claim 3 further comprising:
forming a second photo resist over the first gate stack and the first fin spacers;
etching a second portion of the mask layer directly over the second gate stack and the second semiconductor fins;
etching a second portion the dielectric layer covered by the etched second portion of the mask layer to form the second fin spacers; and
removing the second photo resist after the second recesses are formed.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first epitaxy semiconductor regions and the first gate stack form a first Fin Field-Effect Transistor (FinFET) in a logic device region, and the second epitaxy semiconductor regions and the second gate stack form a FinFET in a Static Random Access Memory (SRAM) device region.

### Claim 6 (depends on 1)

The method of claim 1, wherein the second height of the second fin spacers is higher than about 1.5 times the first height of the first fin spacers.

### Claim 7 (depends on 1)

The method of claim 1, wherein first and the second epitaxy semiconductor regions are both p-type regions.

### Claim 8 (depends on 1)

The method of claim 1, wherein first and the second epitaxy semiconductor regions are both n-type regions.

### Claim 9

A method comprising:
forming first fin spacers on sidewalls of a first semiconductor fin and a second semiconductor fin, wherein the first and the second semiconductor fins have a first distance;
etching the first semiconductor fin and the second semiconductor fin to form first recesses between the first fin spacers;
forming second fin spacers on sidewalls of a third semiconductor fin and a fourth semiconductor fin, wherein the third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance;
etching the third semiconductor fin and the fourth semiconductor fin to form second recesses between the second fin spacers; and
performing an epitaxy to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses, wherein the first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

### Claim 10 (depends on 9)

The method of claim 9, wherein the second distance is smaller than the first distance.

### Claim 11 (depends on 9)

The method of claim 9, wherein the first recesses are between first fin spacers, and the second recesses are between second fin spacers higher than the first fin spacers.

### Claim 12 (depends on 11)

The method of claim 11 further comprising:
forming a dielectric layer covering the first, the second, the third, and the fourth semiconductor fins; and
etching the dielectric layer to form the first fin spacers and the second fin spacers.

### Claim 13 (depends on 12)

The method of claim 12, wherein the first fin spacers and the second fin spacers are formed by separate etching steps.

### Claim 14 (depends on 9)

The method of claim 9, wherein first epitaxy semiconductor regions and the second epitaxy semiconductor regions are source/drain regions of Fin Field-Effect Transistors (FinFETs).

### Claim 15

A method comprising:
in a common deposition process, forming a dielectric layer comprising a first portion on top surfaces and sidewalls of first semiconductor fins and a second portion on top surfaces and sidewalls of second semiconductor fins;
in separate etching processes, etching the first portion of the dielectric layer and the second portion of the dielectric layer to form first fin spacers and second fin spacers, respectively, wherein the first fin spacers have a first height, and the second fin spacers have a second height greater than the first height;
etching the first semiconductor fins to form first recesses between the first fin spacers;
etching the second semiconductor fins to form second recesses between the second fin spacers; and
in a common epitaxy process, growing first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses, wherein the first epitaxy semiconductor regions merge with each other, and the second epitaxy semiconductor regions are discrete from each other.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first semiconductor fins and the second semiconductor fins are etched by different processes.

### Claim 17 (depends on 15)

The method of claim 15 further comprising:
forming a third portion of the dielectric layer on top surfaces and sidewalls of third semiconductor fins;
forming a mask layer covering the first and the second portions of the dielectric layer; and
after the first and the second epitaxy semiconductor regions are formed, removing all of the mask layer covering the dielectric layer.

### Claim 18 (depends on 15)

The method of claim 15, wherein the second height is greater than about 1.5 times the first height.

### Claim 19 (depends on 15)

The method of claim 15, wherein the first and the second epitaxy semiconductor regions are p-type regions.

### Claim 20 (depends on 15)

The method of claim 15, wherein the first and the second epitaxy semiconductor regions are source/drain regions of a logic device and a memory device, respectively.