# US 10,483,265 B2 · Semiconductor device and method for fabricating the same

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- Number: US 10,483,265 B2
- Document ID: US10483265B2
- Status: Granted
- Kind: B2
- Application number: 16/234,181
- Filed: 2018-12-27
- Published: 2019-05-02
- Granted: 2019-11-19
- Earliest claimed: 2017-04-17
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Jeong-Yeop Lee; Dong-Su Park; Jong-Bum Park; Sang-Do Lee; Jae-Min Lee; Kee-Jeung Lee; Jun-Soo Jang
- Web page: https://patentgrep.com/patent/US10483265B2

## CPC

- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 12/033: {the capacitor extending over the transistor}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10D 1/042: {using deposition processes to form electrode extensions}
- H10D 1/043: {using patterning processes to form electrode extensions, e.g. etching}
- H10D 1/696: {comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688)}
- H10D 1/716: {having vertical extensions}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a hybrid pillar-type bottom electrode including a cylindrical first bottom electrode and a pillar-type second bottom electrode filling a cylindrical inside of the cylindrical first bottom electrode;
a supporter suitable for supporting an outer wall of the hybrid pillar-type bottom electrode;
a dielectric layer formed over the hybrid pillar-type bottom electrode and the supporter; and
a top electrode disposed over the dielectric layer,
wherein the cylindrical first bottom electrode includes:
a cylinder body; and
a cylinder head disposed on the cylinder body and having a sloped side wall to have a wider upper surface than the cylinder body.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the pillar-type second bottom electrode includes:
a pillar body filling the cylinder body; and
a pillar head filling the cylinder head and having a sloped side wall to have a wider upper surface than the pillar body.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the pillar-type second bottom electrode includes a pillar body filling the cylinder body, and
an upper surface of the pillar body is disposed at lower level than an upper surface of the cylinder head.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the cylindrical first bottom electrode includes a metal or a metal nitride, and the pillar-type second bottom electrode includes polysilicon.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the cylindrical first bottom electrode comprises a different material than the pillar-type second bottom electrode.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein an upper surface of the cylindrical first bottom electrode and an upper surface of the supporter are at a same level.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein an upper surface of the supporter is disposed at a lower level than an upper surface of the cylindrical first bottom electrode.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein an upper surface of the supporter is disposed at a higher level than an upper surface of the cylindrical first bottom electrode.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the supporter has a multi-level structure including a plurality of supporters supporting an outer wall of the hybrid pillar-type bottom electrode.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein an upper surface of the cylindrical first bottom electrode is disposed substantially coplanar with an upper surface of the multi-level supporter.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein an upper surface of the multi-level supporter is disposed at a lower level than an upper surface of the cylindrical first bottom electrode.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein an upper surface of the multi-level supporter is disposed at a higher level than an upper surface of the cylindrical first bottom electrode.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein the cylinder body has a symmetrical side wall profile and the cylinder head has an asymmetric sidewall profile.