# US 10,483,264 B2 · FinFET CMOS device including single diffusion break in each of NMOS and PMOS regions

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- Number: US 10,483,264 B2
- Document ID: US10483264B2
- Status: Granted
- Kind: B2
- Application number: 15/660,970
- Filed: 2017-07-27
- Published: 2019-01-03
- Granted: 2019-11-19
- Earliest claimed: 2017-06-28
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Yen-Wei Tung; Jen-Yu Wang; Cheng-Tung Huang; Yan-Jou Chen
- Web page: https://patentgrep.com/patent/US10483264B2

## CPC

- H10D 84/853: {comprising FinFETs}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 89/10: Integrated device layouts
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/514: {characterised by the insulating layers}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.

## Claims

### Claim 1

A semiconductor device, comprising:
a first MOS region comprises a PMOS region and a second MOS region comprises a NMOS region on a substrate:
a first fin-shaped structure on the PMOS region;
a first single diffusion break (SDB) structure in the first fin-shaped structure;
a first gate structure on the first SDB structure;
a second gate structure on the first fin-shaped structure, wherein the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region of the first MOS region;
a second fin-shaped structure on the NMOS region;
a second SDB structure in the second fin-shaped structure; and
a third gate structure on the second SDB structure and a fourth gate structure on the second fin-shaped structure, wherein the third gate structure and the fourth gate structure are of same material, the third gate structure disposed directly on top of the second SDB structure is a metal gate and the fourth gate structure disposed on the second fin-shaped structure is also a metal gate in the NMOS region of the second MOS region, wherein each of the metal gates on the PMOS region and the NMOS region is transformed from a dummy gate, while the polysilicon gate is an active gate made of polysilicon.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first SDB structure comprises silicon nitride.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first fin-shaped structure is disposed extending along a first direction and the first SDB structure is disposed extending along a second direction.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the first direction is orthogonal to the second direction.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the second fin-shaped structure is disposed extending along a first direction and the second SDB structure is disposed extending along a second direction.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the first direction is orthogonal to the second direction.