# US 10,483,263 B2 · Semiconductor device and manufacturing method therefor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,263 B2 - Document ID: US10483263B2 - Status: Granted - Kind: B2 - Application number: 15/603,754 - Filed: 2017-05-24 - Published: 2017-12-07 - Granted: 2019-11-19 - Earliest claimed: 2016-06-01 - Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manfacturing International (Beijing) Corp. - Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation - Inventors: Fei Zhou - Web page: https://patentgrep.com/patent/US10483263B2 ## CPC - H10D 84/853: {comprising FinFETs} - H10D 30/024: {of fin field-effect transistors [FinFET]} - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain} - H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling} - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe - H10D 62/8325: {Silicon carbide} - H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions} - H10D 84/0172: {Manufacturing their gate conductors} - H10D 84/0193: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS} - H10P 50/283: {by chemical means} - H10P 50/73: {using masks for insulating materials} - H10P 76/405: {characterised by their composition, e.g. multilayer masks} - H10P 76/4085: {characterised by the processes involved to create the masks} - H10D 64/01306: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon} - H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract The present disclosure provides a semiconductor device and a manufacturing method therefor. The device may include: a semiconductor substrate; a fin projecting from the semiconductor substrate, where trenches are formed on sides of the fin; a first insulator layer partially filling the trenches, where the fin protrudes from the first insulator layer; a second insulator layer covering the fin; a plurality of pseudo gate structures on the second insulator layer, where each pseudo gate structure wraps a part of the fin, where each pseudo gate structure includes a pseudo gate located on the second insulator layer, the plurality of pseudo gate structures includes at least a first pseudo gate structure and a second pseudo gate structure that are spaced from each other, the second pseudo gate structure is located at an edge corner of the fin, and a part of the second pseudo gate structure is on the first insulator layer; spacers, on the first insulator layer and the second insulator layer, at two sides of each of the plurality of pseudo gate structures; and a source or a drain located among the plurality of pseudo gate structures. The present invention can improve reliability of the device. ## Claims ### Claim 1 A manufacturing method for a semiconductor device, comprising: providing a substrate structure, wherein the substrate structure comprises: a semiconductor substrate; a single fin protruding from the semiconductor substrate, wherein trenches are formed on sides of the fin; a pad insulator layer for padding the trenches; a first insulator layer separately formed from the pad insulator layer and partially filling the trenches, wherein the single fin protrudes from the first insulator layer; and a second insulator layer covering the single fin; forming a plurality of pseudo gate structures on the second insulator layer, wherein each pseudo gate structure wraps a part of the single fin, wherein each pseudo gate structure comprises a pseudo gate located on the second insulator layer, wherein the plurality of pseudo gate structures comprises at least a first pseudo gate structure, a second pseudo gate structure, and a third pseudo gate structure that are spaced from each other, and wherein the second pseudo gate structure and the third pseudo gate structure are located at two opposite edge corners of the single fin and the first pseudo gate structure is a only pseudo gate structure disposed between the second pseudo gate structure and the third pseudo gate structure, and a first part of each of the second pseudo gate structure and the third pseudo gate is on and in direct contact with the first insulator layer and a second part of each of the second pseudo gate structure and the third pseudo gate structure is on and in direct contact with the second insulator layer; forming, above the first insulator layer and the second insulator layer, spacers at two sides of each of the second pseudo gate structure and the third pseudo gate structure, where a bottom face of one of the spacers for each of the second pseudo gate structure and the third pseudo gate structure is in direct contact with the first insulator layer whereas a bottom face of another of the spacers for each of the second pseudo gate structure and the third pseudo gate structure is in direct contact with the second insulator layer; etching, after forming the spacers, the second insulator layer and at least a part of the single fin that are not covered by the spacers and the pseudo gates, to form recesses in the single fin; and forming at least one source or drain in the recesses. ### Claim 2 (depends on 1) The manufacturing method for a semiconductor device according to claim 1, wherein the step of forming recesses comprises: forming, in the single fin, a first recess located between the first pseudo gate structure and the second pseudo gate structure and forming a second recess located between the first pseudo gate structure and the third pseudo gate structure through etching. ### Claim 3 (depends on 2) The manufacturing method for a semiconductor device according to claim 2, wherein the step of forming at least one source or drain in the recess comprises: forming a source in the first recess and forming a drain in the second recess. ### Claim 4 (depends on 1) The manufacturing method for a semiconductor device according to claim 1, wherein material of the pseudo gates comprises polysilicon. ### Claim 5 (depends on 1) The manufacturing method for a semiconductor device according to claim 1, further comprising forming a hard mask layer on each of the pseudo gate structures, wherein material of the hard mask layer comprises silicon nitride. ### Claim 6 (depends on 1) The manufacturing method for a semiconductor device according to claim 1, wherein the second pseudo gate structure is spaced from the first pseudo gate structure for a first distance, wherein the first distance ranges from 60 nm to 100 nm. ### Claim 7 (depends on 1) The manufacturing method for a semiconductor device according to claim 1, wherein the third pseudo gate structure is spaced from the first pseudo gate structure for a second distance, wherein the second distance ranges from 60 nm to 100 nm. ### Claim 8 (depends on 5) The manufacturing method for a semiconductor device according to claim 5, further comprising: forming an interlayer dielectric layer to cover the substrate structure after the source or the drain is formed; etching back the interlayer dielectric layer, to expose an upper surface of the hard mask layer; removing the hard mask layer, the pseudo gates, and a part of the second insulator layer, so as to form openings; and forming gate structures in the opening. ### Claim 9 (depends on 8) The manufacturing method for a semiconductor device according to claim 8, wherein each of the gate structures comprises: a gate insulator layer that is on the single fin and wraps a part of the single fin, and a gate on the gate insulator layer. ### Claim 10 (depends on 1) The manufacturing method for a semiconductor device according to claim 1, wherein the single fin is an N-well region, and material of the at least one source or the drain comprises silicon germanium; or the single fin is a P-well region, and material of the at least one source or the drain comprises silicon carbide. ### Claim 11 (depends on 1) The manufacturing method for a semiconductor device according to claim 1, wherein the semiconductor substrate comprises two single fins, with a first single fin for forming a PMOS device and a second single fin for forming an NMOS device, and wherein material of the at least one source or the drain on the first single fin comprises silicon germanium; and material of the at least one source or the drain on the second single fin comprises silicon carbide. ### Claim 12 A semiconductor device, comprising: a semiconductor substrate; a single fin protruding from the semiconductor substrate, wherein trenches are formed on sides of the single fin; a pad insulator layer for padding the trenches; a first insulator layer separately formed from the pad insulator layer and partially filling the trenches, wherein the single fin protrudes from the first insulator layer; a second insulator layer covering the single fin; a plurality of pseudo gate structures on the second insulator layer, wherein each pseudo gate structure wraps a part of the single fin, wherein each pseudo gate structure comprises a pseudo gate located on the second insulator layer, wherein the plurality of pseudo gate structures comprises at least a first pseudo gate structure, a second pseudo gate structure, and a third pseudo gate structure that are spaced from each other, and wherein the second pseudo gate structure and the third pseudo gate structure are located at two opposite edge corners of the single fin and the first pseudo gate structure is a only pseudo gate structure disposed between the second pseudo gate structure and the third pseudo gate structure, and a first part of each of the second pseudo gate structure and the third pseudo gate is on and in direct contact with the first insulator layer and a second part of each of the second pseudo gate structure and the third pseudo gate structure is on and in direct contact with the second insulator layer; spacers at two sides of each of the second pseudo gate structure and the third pseudo gate structure, where a bottom face of one of the spacers for each of the second pseudo gate structure and the third pseudo gate structure is in direct contact with the first insulator layer whereas a bottom face of another of the spacers for each of the second pseudo gate structure and the third pseudo gate structure is in direct contact with the second insulator layer; and at least one source or drain on the single fin and located among the plurality of pseudo gate structures. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein material of the pseudo gates comprises polysilicon. ### Claim 14 (depends on 12) The semiconductor device according to claim 12, further comprising a hard mask layer on each of the pseudo gate structures wherein material of the hard mask layer comprises silicon nitride. ### Claim 15 (depends on 12) The semiconductor device according to claim 12, wherein the second pseudo gate structure is spaced from the first pseudo gate structure for a first distance, wherein the first distance ranges from 60 nm to 100 nm. ### Claim 16 (depends on 12) The semiconductor device according to claim 12, wherein the third pseudo gate structure is spaced from the first pseudo gate structure for a second distance, wherein the second distance ranges from 60 nm to 100 nm. ### Claim 17 (depends on 12) The semiconductor device according to claim 12, wherein the at least one source or drain comprises a source located between the first pseudo gate structure and the second pseudo gate structure and a drain located between the first pseudo gate structure and the third pseudo gate structure. ### Claim 18 (depends on 12) The semiconductor device according to claim 12, wherein the single fin is an N-well region, and material of the at least one source or the drain comprises silicon germanium; or the single fin is a P-well region, and material of the at least one source or the drain comprises silicon carbide. ### Claim 19 (depends on 12) The semiconductor device according to claim 12, wherein the semiconductor device comprises two single fins, with a first single fin for forming a PMOS device and a second single fin for forming an NMOS device, wherein material of the at least one source or the drain on the first single fin comprises silicon germanium; and wherein material of the at least one source or the drain on the second single fin comprises silicon carbide.