# US 10,483,261 B2 · Integrated circuit having chemically modified spacer surface

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- Number: US 10,483,261 B2
- Document ID: US10483261B2
- Status: Granted
- Kind: B2
- Application number: 15/447,795
- Filed: 2017-03-02
- Published: 2017-06-22
- Granted: 2019-11-19
- Earliest claimed: 2011-03-28
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Brian K. Kirkpatrick; Amitabh Jain
- Web page: https://patentgrep.com/patent/US10483261B2

## CPC

- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 64/514: {characterised by the insulating layers}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/6905: {being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H}
- H10P 14/6927: {the material being a silicon oxynitride, e.g. SiON or SiON:H}
- H10P 50/242: {of Group IV materials}
- H10P 50/283: {by chemical means}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of fabricating an integrated circuit includes depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon including a gate electrode on a gate dielectric. The first dielectric material is etched to form sidewall spacers on sidewalls of the gate stack. A top surface of the first dielectric material is chemically converted to a second dielectric material by adding at least one element to provide surface converted sidewall spacers. The second dielectric material is chemically bonded across a transition region to the first dielectric material.

## Claims

### Claim 1

An integrated circuit (IC), comprising:
sidewall spacers having a second dielectric material on a first dielectric material, wherein the second dielectric material comprises carbon and silicon and the first dielectric material comprises silicon and another element besides carbon, and wherein the second dielectric material is chemically bonded across a transition region to the first dielectric material,
wherein the transition region has a composition that includes silicon, carbon and the another element besides carbon, and
wherein at a widest point of the sidewall spacers, the transition region is thicker than the second dielectric material.

### Claim 2 (depends on 1)

The IC of claim 1, wherein the first dielectric material comprises silicon nitride and the second dielectric material comprises (SiC), silicon carbonitride (SiCN) or silicon oxy-carbonitride (SiOCN).

### Claim 3 (depends on 1)

The IC of claim 1, wherein a total thickness of each of the sidewall spacers is ≤100 Angstroms.

### Claim 4 (depends on 1)

The IC of claim 1, further comprising:
a gate stack on a substrate, the gate stack including a gate electrode on a gate dielectric; and
wherein the sidewall spacers are on sidewalls of the gate stack.

### Claim 5 (depends on 4)

The IC of claim 4, wherein the first dielectric material comprises silicon nitride and the second dielectric material comprises silicon carbonitride (SiCN).

### Claim 6 (depends on 4)

The IC of claim 4, wherein the first dielectric material comprises silicon nitride and the second dielectric material comprises silicon oxy-carbonitride (SiOCN).

### Claim 7 (depends on 4)

The IC of claim 4, wherein a thickness of the sidewall spacers is ≤100 Angstroms.

### Claim 8 (depends on 1)

The IC of claim 1, wherein the transition region has decreasing carbon content from the second dielectric material to the first dielectric material.

### Claim 9 (depends on 1)

The IC of claim 1, wherein the transition region has increasing nitrogen content from the second dielectric material to the first dielectric material.

### Claim 10

An integrated circuit (IC), comprising:
a semiconductor substrate having a surface; and
at least one metal-oxide-semiconductor (MOS) transistor at the surface, the MOS transistor comprising:
gate stack including a gate electrode on a gate dielectric; and
sidewall spacers on sidewalls of the gate stack, the sidewall spacers comprising a second dielectric material, a first dielectric material, and a transition region between the second dielectric material and the first dielectric material, wherein the second dielectric material comprises carbon and silicon and the first dielectric material comprises silicon and another element besides carbon,
wherein the transition region has a composition that includes silicon, carbon and the another element besides carbon, and
wherein the second dielectric material is chemically bonded across the transition region to the first dielectric material, wherein at a widest point of the sidewall spacers, the transition region is in the range of 15-25 Angstroms thick.

### Claim 11 (depends on 10)

The IC of claim 10, wherein the first dielectric material comprises silicon nitride and the second dielectric material comprises silicon carbonitride (SiCN).

### Claim 12 (depends on 10)

The IC of claim 10, wherein the first dielectric material comprises silicon nitride and the second dielectric material comprises silicon oxy-carbonitride (SiOCN).

### Claim 13 (depends on 10)

The IC of claim 10, wherein the first dielectric material comprises silicon nitride and the second dielectric material comprises silicon carbide (SiC).

### Claim 14 (depends on 10)

The IC of claim 10, wherein a total thickness of each of the sidewall spacers is ≤100 Angstroms.

### Claim 15 (depends on 10)

The IC of claim 10, wherein the transition region has decreasing carbon content and increasing nitrogen content from the second dielectric material to the first dielectric material.