# US 10,483,260 B2 · Semiconductor carrier with vertical power FET module

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- Number: US 10,483,260 B2
- Document ID: US10483260B2
- Status: Granted
- Kind: B2
- Application number: 15/675,939
- Filed: 2017-08-14
- Published: 2018-07-05
- Granted: 2019-11-19
- Earliest claimed: 2010-06-24
- Applicants: L. Pierre de Rochemont
- Inventors: L. Pierre de Rochemont
- Web page: https://patentgrep.com/patent/US10483260B2

## CPC

- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 12/441: {Vertical IGBTs}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 84/141: {VDMOS having built-in components}
- H10D 84/143: {the built-in components being PN junction diodes}
- H10W 44/501: {Inductive arrangements (H10W44/20 takes precedence)}
- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- H10W 90/00: Package configurations
- H01F 17/06: with core substantially closed in itself, e.g. toroid
- H01F 27/2804: {Printed windings}
- H01F 30/16: Toroidal transformers
- H02M 3/28: using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
- H10D 62/402: {Amorphous materials}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- Y10T 428/12493: Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

A monolithic power management module provides a chip carrier with surfaces, ground traces, signal and power interconnects; a three dimensional FET formed on the chip carrier to modulate currents through the carrier or on the carrier surface; a toroidal inductor or transformer coil with a ceramic magnetic core formed on the chip carrier adjacent to the FET and having a first winding connected to the FET, and a plurality of passive ceramic components formed on the chip carrier surface.

## Claims

### Claim 1

A monolithic power management module, comprising:
a chip carrier further comprising surfaces, ground traces, signal and power interconnects;
a three dimensional FET formed on the chip carrier to modulate currents through the chip carrier or on the surfaces;
a toroidal inductor or transformer coil with a ceramic magnetic core formed on the chip carrier adjacent to the three dimensional FET and having a first winding connected to the three dimensional FET, and
a plurality of passive ceramic components formed on the chip carrier surfaces including clock circuitry in a form of an LCR resonator further comprising an inductor coil, a capacitive element and a resistive element; and
wherein the three dimensional FET includes an elongated gate electrode comprising a conductor that forms a resonant transmission line by configuring the conductor to form a serpentine electrode that contains a capacitive element determined by charge-collected beneath the gate, a resistive dement determined by the conductor, length and cross-sectional area, of the conductor used to form the serpentine electrode, and an Inductive element formed by half-turns that loop the serpentine electrode winding back upon itself.

### Claim 2 (depends on 1)

The module of claim 1, wherein the chip carrier is a semiconducting substrate comprising a plurality of active components formed on or in the carrier.

### Claim 3 (depends on 1)

The module of claim 1, further comprising one or more semiconductor die mounted on the carrier that are electrically connected with the power management module.

### Claim 4 (depends on 2)

The module of claim 2, further comprising a semiconducting substrate that contains a variety of low-level sensing, latching and bus circuitry integrated on or into its surface.

### Claim 5 (depends on 1)

The module of claim 1, wherein the clock circuitry comprises a high-Q LCR resonator encapsulated within amorphous silica.

### Claim 6 (depends on 1)

The module of claim 1, wherein the clock circuitry comprises a high-Q LCR resonator formed on an amorphous silica block.

### Claim 7 (depends on 6)

The module of claim 6, wherein the chip carrier is a semiconducting substrate that further comprises a phase-locked loop array mounted on or embedded within the chip carrier.

### Claim 8 (depends on 7)

The module of claim 7, wherein the self-resonance frequency of the high-Q LCR resonator is altered by a switching element integrated into the chip carrier semiconductor substrate that routes the timing signal through different turns of the inductor coil.

### Claim 9 (depends on 3)

The module of claim 3, wherein the passive ceramic components maintain a tolerance that varies ±1% from their specified performance value over standard operating temperatures.

### Claim 10 (depends on 9)

The module of claim 9, wherein the semiconductor die mounted on the carrier comprise fewer redundant transistor assemblies in the semiconductor die than needed when the semiconductor die are electrically connected to interconnect circuitry generating signals tuned by loose tolerance components.

### Claim 11 (depends on 10)

The module of claim 10, wherein the chip carrier is a semiconducting chip carrier comprising active circuitry embedded within the carrier substrate.