# US 10,483,259 B2 · Series resistor over drain region in high voltage device

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- Number: US 10,483,259 B2
- Document ID: US10483259B2
- Status: Granted
- Kind: B2
- Application number: 15/942,728
- Filed: 2018-04-02
- Published: 2018-08-09
- Granted: 2019-11-19
- Earliest claimed: 2014-03-13
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Ker Hsiao Huo; Fu-Chih Yang; Chun Lin Tsai; Yi-Min Chen; Chih-Yuan Chan
- Web page: https://patentgrep.com/patent/US10483259B2

## CPC

- H10D 89/911: {using passive elements as protective elements}
- H10D 1/47: Resistors having no potential barriers
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 64/115: {Resistive field plates, e.g. semi-insulating field plates}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0156: {Manufacturing their doped wells}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 84/817: {Combinations of field-effect devices and resistors only}
- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10W 20/498: {Resistive arrangements or effects of, or between, wiring layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Some embodiments relate to an integrated circuit. The integrated circuit includes a ring-shaped drain region having an inner edge and an outer edge. A channel region surrounds the ring-shaped drain region. A source region surrounds the channel region. The channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and is separated from the channel region by a gate dielectric. An inner edge of the gate electrode is proximate to the drain region. A resistor structure is arranged over and spaced apart from an upper surface of the substrate. The resistor structure has a first end and a second end which are connected by a curved or polygonal path of resistive material. The first end is coupled to the ring-shaped drain. The resistor has an outer perimeter that is surrounded by the inner edge of the ring-shaped drain region.

## Claims

### Claim 1

A semiconductor device, comprising:
a transistor, comprising:
a ring-shaped drain region disposed in a substrate, the ring-shaped drain region having an inner edge and an outer edge;
a channel region disposed in the substrate and surrounding the ring-shaped drain region;
a source region disposed in the substrate and surrounding the channel region, wherein the channel region separates the drain region from the source region; and
a gate electrode arranged over the channel region, the gate electrode separated from the channel region by a gate dielectric, and having an inner edge proximate to the drain region; and
a resistor structure arranged in series with the transistor, the resistor structure arranged over the substrate and perimeterally bounded by the inner edge of the ring-shaped drain region, the resistor structure having a first end and a second end which are connected by a curved or polygonal path of resistive material, wherein the first end is electrically coupled to the ring-shaped drain region, and the second end is electrically-isolated from the gate electrode and the source region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a field oxide region surrounded by the ring-shaped drain region, wherein the resistor structure is disposed on an upper surface of the field oxide region.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the resistor structure comprises polysilicon.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the curved or polygonal path is spiral shaped with multiple windings, and wherein outer windings of the curved or polygonal path surround inner windings of the curved or polygonal path.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the curved or polygonal path is C-shaped.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the resistor structure exhibits an absence of sharp corners as viewed from above.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising:
a drain contact extending upwards from the ring-shaped drain region;
a metal interconnect layer coupled to the drain contact and extending horizontally over the substrate; and
a contact or via extending downward from the metal interconnect layer to the curved or polygonal path of resistive material.

### Claim 8

An integrated circuit, comprising:
a ring-shaped drain region disposed in a substrate, the ring-shaped drain region having an inner edge and an outer edge;
a channel region surrounding the ring-shaped drain region;
a source region surrounding the channel region, wherein the channel region separates the ring-shaped drain region from the source region;
a gate electrode arranged over the channel region, the gate electrode separated from the channel region by a gate dielectric and having an inner edge proximate to the ring-shaped drain region; and
a resistor structure arranged over and spaced apart from an upper surface of the substrate, the resistor structure having a first end and a second end which are connected by a curved or polygonal path of resistive material, the first end being coupled to the ring-shaped drain region, and the resistor structure having an outer perimeter that is surrounded by the inner edge of the ring-shaped drain region.

### Claim 9 (depends on 8)

The integrated circuit of claim 8, further comprising:
a dielectric region arranged in a center opening of the ring-shaped drain region, wherein the resistor structure is disposed on an upper surface of the dielectric region and wherein the outer perimeter of the resistor structure is bounded by an outer edge of the dielectric region.

### Claim 10 (depends on 8)

The integrated circuit of claim 8, further comprising:
a drain contact extending upwards from the ring-shaped drain region;
a metal interconnect layer coupled to the drain contact and extending horizontally over the substrate; and
a contact or via extending downward from the metal interconnect layer to the curved or polygonal path of resistive material.

### Claim 11 (depends on 8)

The integrated circuit of claim 8, wherein the resistor structure has a resistance between approximately 20 ohms and approximately 50 ohms.

### Claim 12 (depends on 8)

The integrated circuit of claim 8, wherein the resistor structure comprises polysilicon.

### Claim 13 (depends on 8)

The integrated circuit of claim 8, wherein the curved or polygonal path is spiral shaped with multiple windings, and wherein outer windings of the curved or polygonal path surround inner windings of the curved or polygonal path.

### Claim 14 (depends on 8)

The integrated circuit of claim 8, wherein the curved or polygonal path is C-shaped.

### Claim 15 (depends on 8)

The integrated circuit of claim 8, wherein the resistor structure exhibits an absence of sharp corners as viewed from above.

### Claim 16

An integrated circuit, comprising:
a circular field oxide region disposed on an upper surface of a semiconductor substrate;
a ring-shaped drain region disposed in the semiconductor substrate and having an inner circumference and an outer circumference, the inner circumference of the ring-shaped drain region corresponding to an outer circumference of the circular field oxide region;
a ring-shaped channel region disposed in the semiconductor substrate and concentrically surrounding the ring-shaped drain region;
a ring-shaped source region disposed in the semiconductor substrate and concentrically surrounding the ring-shaped channel region, the ring-shaped channel region separating the ring-shaped drain region from the ring-shaped source region;
a ring-shaped gate electrode arranged over the channel region and having an inner gate circumference and an outer gate circumference, the ring-shaped gate electrode separated from the ring-shaped channel region by a gate dielectric;
a resistor structure arranged over the circular field oxide region and perimeterally bounded by the inner circumference of the ring-shaped drain region, the resistor structure having a first end and a second end which are connected by a curved or polygonal path of resistive material;
a drain contact extending upwards from the ring-shaped drain region;
a metal interconnect layer coupled to the drain contact and extending horizontally over the semiconductor substrate; and
a contact or via extending downward from the metal interconnect layer to the curved or polygonal path of resistive material.

### Claim 17 (depends on 16)

The integrated circuit of claim 16, wherein the resistor structure has a resistance between approximately 20 ohms and approximately 50 ohms.

### Claim 18 (depends on 16)

The integrated circuit of claim 16, wherein the resistor structure comprises polysilicon.

### Claim 19 (depends on 16)

The integrated circuit of claim 16, wherein the curved or polygonal path is spiral shaped with multiple windings, and wherein outer windings of the curved or polygonal path surround inner windings of the curved or polygonal path.

### Claim 20 (depends on 16)

The integrated circuit of claim 16, wherein the curved or polygonal path is C-shaped.