# US 10,483,258 B2 · Semiconductor devices and methods to enhance electrostatic discharge (ESD) robustness, latch-up, and hot carrier immunity

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- Number: US 10,483,258 B2
- Document ID: US10483258B2
- Status: Granted
- Kind: B2
- Application number: 15/899,117
- Filed: 2018-02-19
- Published: 2018-08-30
- Granted: 2019-11-19
- Earliest claimed: 2017-02-25
- Assignees: Indian Institute of Science
- Applicants: Indian Institute of Science
- Inventors: Mayank Shrivastava; Milova Paul; Harald Gossner
- Web page: https://patentgrep.com/patent/US10483258B2

## CPC

- H10D 89/811: {using FETs as protective elements}
- H10D 18/251: {Lateral thyristors}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/852: {comprising forksheet IGFETs}
- H10D 84/853: {comprising FinFETs}
- H10D 84/854: {comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 89/713: {including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure relates to non-planar ESD protection devices. The present disclosure provides a device structure and method of fabricating the structure that is essentially immune to latch-up and possess high ESD robustness and reliability. In an aspect, the present disclosure provides a mixed silicidation and selective epitaxy (epi) FinFET processes for latch-up immunity together with ESD robustness, thereby allowing achievement of ESD efficient parasitic structures together with latch-up immune and reliable functional devices. The present disclosure provides a dual silicidation scheme where ESD protection element(s) have fins that are partially silicided, and functional devices have fins that are fully silicided. The present disclosure also provides a hybrid contact and junction profile scheme where ESD protection element(s) have fins that are partially silicided with or without deep junctions depending on their application, and functional devices have fins that are fully silicided with the silicide edge crossing the junction. On the other hand, a dual Epi scheme is implemented such that ESD protection elements have fins with Epi contact, and functional devices have fins that are fully silicided without Epi (raised S/D) contact.

## Claims

### Claim 1

A semiconductor device comprising at least one ESD protection device and at least one functional device, wherein the at least one ESD protection device comprises one or more fins partially silicided having a selective epitaxial growth before a silicidation, and wherein the at least one functional device comprises one or more fins fully silicided without an epitaxial growth.

### Claim 2

A semiconductor device comprising at least one ESD protection device and at least one functional device, wherein the at least one ESD protection device comprises one or more fins having a selective epitaxial growth before a silicidation, and wherein the at least one functional device comprises one or more fins fully silicided, without an epitaxial growth.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein said semiconductor device comprises one or more guard rings.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein said semiconductor device comprises at least one fin made of a nanowire or an array of nanowires on top of each other.

### Claim 5 (depends on 2)

The semiconductor device of claim 2, wherein said semiconductor device comprises at least one fin made of any or a combination of Si, SiGe, and Ge, materials belonging to III-V or III-Nitride groups, transition metal dichalcogenides or other 2-Dimensional semiconductors.

### Claim 6 (depends on 2)

The semiconductor device of claim 2, wherein the semiconductor device comprises a 3D structure repeated in X and Y directions so as to create devices with larger electrical widths.

### Claim 7 (depends on 2)

The semiconductor device of claim 2, wherein the semiconductor device comprises a substrate selected from any or a combination of a semiconductor, an insulator, and a stack of the semiconductor and the insulator.

### Claim 8 (depends on 2)

An integrated circuit made of semiconductor device of claim 2.