# US 10,483,253 B1 · Display with embedded pixel driver chips

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- Number: US 10,483,253 B1
- Document ID: US10483253B1
- Status: Granted
- Kind: B1
- Application number: 15/247,249
- Filed: 2016-08-25
- Granted: 2019-11-19
- Earliest claimed: 2015-09-24
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Hsin-Hua Hu
- Web page: https://patentgrep.com/patent/US10483253B1

## CPC

- H10W 90/00: Package configurations
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/685: comprising multiple insulating layers
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10H 29/142: {Two-dimensional arrangements, e.g. asymmetric LED layout}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/652: Cross-sectional shapes
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/874: {On different surfaces}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/9413: {on encapsulations}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS

## Abstract

Embodiments describe a display integration scheme in which an array of pixel driver chips embedded front side up in an insulator layer. A front side redistribution layer (RDL) spans across and is in electrical connection with the front sides of the array of pixel driver chips, and an array of light emitting diodes (LEDs) is bonded to the front side RDL. The pixel driver chips may be located directly beneath the display area of the display panel.

## Claims

### Claim 1

A display panel comprising:
an array of pixel driver chips embedded front side up in an insulator layer;
a front side redistribution layer (RDL) spanning across and in electrical connection with front sides of the array of pixel driver chips; and
an array of light emitting diodes (LEDs) bonded to the front side RDL, the array of LEDs arranged in an array of pixels, wherein each pixel driver chip is to switch and drive a plurality of LEDs in the array of LEDs for a plurality of pixels;
wherein each pixel driver chip has a minimum x-y dimension that that is larger than a maximum pitch in the x-y dimension between adjacent LEDs of the array of LEDs, and each pixel driver chip is characterized by pixel driver chip area in x-y dimensions that is directly underneath an entire LED area in the x-y dimensions for each of a corresponding plurality of LEDs of the array of LEDs.

### Claim 2 (depends on 1)

The display panel of claim 1, further comprising a back side RDL spanning across the insulator layer and the array of pixel driver chips.

### Claim 3 (depends on 2)

The display panel of claim 2, further comprising a plurality of conductive pillars extending through the insulator layer from the back side RDL to the front side RDL.

### Claim 4 (depends on 3)

The display panel of claim 3, further comprising a plurality of device chips mounted on the back side RDL and in electrical connection with the plurality of conductive pillars.

### Claim 5 (depends on 1)

The display panel of claim 1, wherein each pixel driver chip comprises an analog driving circuit.

### Claim 6 (depends on 5)

The display panel of claim 5, wherein each pixel driver chip comprises a storage capacitor.

### Claim 7 (depends on 1)

The display panel of claim 1, wherein each pixel driver chip comprises digital driving circuit.

### Claim 8 (depends on 7)

The display panel of claim 7, each pixel driver chip comprises a data storage element.

### Claim 9 (depends on 1)

The display panel of claim 1, further comprising a plurality of row driver chips.

### Claim 10 (depends on 9)

The display panel of claim 9, wherein the plurality of row driver chips are embedded front side up in the insulator layer.

### Claim 11 (depends on 9)

The display panel of claim 9, wherein the plurality of row driver chips are bonded to the front side RDL outside of a display area.

### Claim 12 (depends on 9)

The display panel of claim 9, further comprising a back side RDL spanning across the insulator layer and the array of pixel driver chips, wherein the plurality of row driver chips are bonded to the back side RDL.

### Claim 13 (depends on 2)

The display panel of claim 2, further comprising a device chip including a timing controller bonded to the back side RDL.

### Claim 14 (depends on 1)

The display panel of claim 1, wherein each LED is formed of an inorganic semiconductor-based material.

### Claim 15 (depends on 1)

The display panel of claim 1, wherein each LED has a maximum lateral dimension of 1 to 300 μm.

### Claim 16 (depends on 1)

The display panel of claim 1, wherein each LED has a maximum lateral dimension of 1 to 20 μm.

### Claim 17 (depends on 1)

The display panel of claim 1, further comprising a passivation layer laterally surrounding each LED of the array of LEDs.

### Claim 18 (depends on 17)

The display panel of claim 17, further comprising a plurality of transparent top conductive contact layers formed over the passivation layer and the array of LEDs to make electrical contact with the array of LEDs.

### Claim 19 (depends on 1)

The display panel of claim 1, wherein the front side RDL includes a plurality of dielectric layers and a plurality of redistribution lines.