# US 10,483,249 B2 · Integrated passive devices on chip > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,249 B2 - Document ID: US10483249B2 - Status: Granted - Kind: B2 - Application number: 16/060,658 - Filed: 2015-12-26 - Published: 2019-01-03 - Granted: 2019-11-19 - Earliest claimed: 2015-12-26 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Donald S. Gardner; Edward A. Burton; Gerhard Schrom; Larry E. Mosley - Web page: https://patentgrep.com/patent/US10483249B2 ## CPC - H10W 90/00: Package configurations - H10D 1/042: {using deposition processes to form electrode extensions} - H10D 1/20: Inductors - H10D 1/68: Capacitors having no potential barriers - H10D 1/714: {having horizontal extensions} - H10D 1/716: {having vertical extensions} - H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 95/00: Packaging processes not covered by the other groups of this subclass - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Embodiments are generally directed to integrated passive devices on chip. An embodiment of a device includes a semiconductor die; a semiconductor die package, a first side of the package being coupled with the semiconductor die; and one or more separate dies to provide passive components for operation of the semiconductor die, wherein the passive components for operation of the semiconductor die includes inductors. ## Claims ### Claim 1 A device comprising: a semiconductor die; a semiconductor die package, a first side of the package being coupled with the semiconductor die; and one or more separate dies to provide a plurality of passive components for operation of the semiconductor die, wherein the plurality of passive components for operation of the semiconductor die includes a plurality of inductors and a plurality of capacitors, and wherein a first separate die includes a first set of passive components on a first side of the first separate die and a second, different set of passive components on a second, opposite side of the first separate die. ### Claim 2 (depends on 1) The device of claim 1, wherein the one or more separate dies further include one or more high voltage transistors. ### Claim 3 (depends on 2) The device of claim 2, wherein the one or more high voltage transistors includes one or more GaN (gallium nitride) transistors. ### Claim 4 (depends on 1) The device of claim 1, wherein the one or more separate dies are coupled with a second, opposite side of the package and are electrically connected with the semiconductor die through the package. ### Claim 5 (depends on 4) The device of claim 4, further comprising a motherboard, the one or more separate dies being coupled between the package and the motherboard, the package being connected to the motherboard by solder balls. ### Claim 6 (depends on 1) The device of claim 1, further comprising an interposer between the semiconductor die and the semiconductor die package, wherein the one or more separate dies are embedded inside the interposer. ### Claim 7 (depends on 1) The device of claim 1, wherein the first side of the first separate die includes a set of a first type of capacitor and a set of inductors, and the second side of the first separate die includes a set of a second type of capacitor. ### Claim 8 (depends on 7) The device of claim 7, wherein the first type of capacitor is a two dimensional planar capacitor. ### Claim 9 (depends on 7) The device of claim 7, wherein the first separate die includes a porous material, and wherein the second type of capacitor includes a three dimensional capacitor formed in the pores of the porous material. ### Claim 10 (depends on 9) The device of claim 9, wherein the three dimensional capacitor is a MIM (metal-insulator-metal) capacitor. ### Claim 11 (depends on 1) The device of claim 1, wherein the semiconductor die is system on chip (SoC). ### Claim 12 A method comprising: fabricating one or more separate dies, the one or more separate dies including a plurality of passive components; coupling a first side of a semiconductor die package with a semiconductor die; and coupling the one or more separate dies with the semiconductor die package to provide passive components for operation of the semiconductor die; wherein the plurality of passive components includes one or more inductors and a plurality of capacitors; and wherein fabricating the one or more separate dies includes fabricating a first separate die with a first set of passive components on a first side of the first separate die and a second, different set of passive components on a second, opposite side of the first separate die. ### Claim 13 (depends on 12) The method of claim 12, wherein the one or more separate dies further include one or more high voltage transistors. ### Claim 14 (depends on 12) The method of claim 12, wherein coupling the one or more separate dies with the semiconductor die package includes coupling the one or more separate dies with a second, opposite side of the package, and electrically connected the one or more separate dies with the semiconductor die through the package. ### Claim 15 (depends on 12) The method of claim 12, wherein the first side of the first separate die includes a set of a first type of capacitor and a set of inductors, and the second side of the first separate die includes a set of a second type of capacitor. ### Claim 16 (depends on 15) The method of claim 15, wherein the first type of capacitor is a two dimensional planar capacitor. ### Claim 17 (depends on 15) The method of claim 15, wherein fabricating the one or more separate dies includes fabricating a porous material on the second side of the first separate die and fabricating a three dimensional capacitor in the pores of the porous material. ### Claim 18 (depends on 17) The method of claim 17, wherein fabricating the three dimensional capacitor includes fabricating one or more MIM (metal-insulator-metal) capacitors. ### Claim 19 A system comprising: a system on chip; a semiconductor die package, a first side of the package being coupled with the system on chip; one or more separate dies to provide a plurality of passive components for operation of the system on chip, a first side of each of the one or more separate dies being coupled to a second, opposite side of semiconductor die package; a mother board, the motherboard being coupled with the second side of the semiconductor die package and a second, opposite side of each of the one or more separate dies, the one or more separate dies being between the semiconductor die package and the motherboard; wherein the plurality of passive components includes a plurality of inductors, wherein the one or more separate dies further include one or more high voltage transistors. ### Claim 20 (depends on 19) The system of claim 19, the plurality of passive components further includes a plurality of capacitors. ### Claim 21 A device comprising: a semiconductor die; a semiconductor die package, a first side of the package being coupled with the semiconductor die; and one or more separate dies to provide a plurality of passive components for operation of the semiconductor die, wherein the one or more separate dies further include one or more high voltage transistors, and wherein the plurality of passive components for operation of the semiconductor die includes a plurality of inductors. ### Claim 22 (depends on 21) The device of claim 21, wherein the one or more high voltage transistors includes one or more GaN (gallium nitride) transistors. ### Claim 23 A device comprising: a semiconductor die; a semiconductor die package, a first side of the package being coupled with the semiconductor die; one or more separate dies to provide a plurality of passive components for operation of the semiconductor die, wherein the plurality of passive components for operation of the semiconductor die includes a plurality of inductors; and an interposer between the semiconductor die and the semiconductor die package, wherein the one or more separate dies are embedded inside the interposer. ### Claim 24 A method comprising: fabricating one or more separate dies, the one or more separate dies including a plurality of passive components; coupling a first side of a semiconductor die package with a semiconductor die; and coupling the one or more separate dies with the semiconductor die package to provide passive components for operation of the semiconductor die, wherein the one or more separate dies further include one or more high voltage transistors, and wherein the plurality of passive components includes one or more inductors.