# US 10,483,247 B2 · Semiconductor device, display panel, and method for manufacturing display panel

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- Number: US 10,483,247 B2
- Document ID: US10483247B2
- Status: Granted
- Kind: B2
- Application number: 16/083,134
- Filed: 2017-03-07
- Published: 2019-04-18
- Granted: 2019-11-19
- Earliest claimed: 2016-03-08
- Assignees: LG Innotek Co., Ltd.
- Applicants: LG Innotek Co., Ltd.
- Inventors: Sang Youl Lee; Chung Song Kim; Ji Hyung Moon; Sun Woo Park; June O Song
- Web page: https://patentgrep.com/patent/US10483247B2

## CPC

- H10W 90/00: Package configurations
- H10H 20/018: {Bonding of wafers}
- H10H 20/80: Constructional details
- H10H 20/819: characterised by their shape, e.g. curved or truncated substrates
- H10H 20/853: characterised by their shape
- H10H 20/855: Optical field-shaping means, e.g. lenses
- H10H 20/857: Interconnections, e.g. lead-frames, bond wires or solder balls
- H10H 20/036: {of packages}
- H10H 20/0362: {of encapsulations}
- H10H 29/142: {Two-dimensional arrangements, e.g. asymmetric LED layout}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS

## Abstract

The semiconductor element according to an embodiment comprises: a light-emitting structure comprising a p-type semiconductor layer, an active layer disposed under the p-type semiconductor layer, and an n-type semiconductor layer disposed under the active layer; a protective layer disposed on the side surface and upper surface of the light-emitting structure; a p-type contact layer disposed over the p-type semiconductor layer; and an n-type contact layer disposed under the n-type semiconductor layer, wherein: the width of the lower surface of the n-type semiconductor layer is provided greater than that of the lower surface of the p-type semiconductor layer; the width of the upper surface of the n-type contact layer is provided greater than that of the upper surface of the n-type semiconductor layer; and the angle between the lower surface of the n-type semiconductor layer and the side surface of the light-emitting structure may be 30-80 degrees.

## Claims

### Claim 1

A method for manufacturing a display panel, the method comprising:
forming a semiconductor layer on a growth substrate, the semiconductor layer comprising an n-type semiconductor layer, an active layer formed on the n-type semiconductor layer, and a p-type semiconductor layer formed on the active layer;
performing an isolation process of isolating the semiconductor layer into a plurality of light-emitting structures to expose the n-type semiconductor layer between the plurality of light-emitting structures;
forming a protection layer on side and upper surfaces of each of the plurality of light emitting structures;
forming a p-type contact layer contacting the p-type semiconductor layer of each of the plurality of light-emitting structures;
forming a sacrificial layer between the side surfaces of the plurality of light-emitting structures and on the p-type contact layer;
attaching a first temporary substrate on the sacrificial layer by using an adhesion layer and separating the growth substrate;
etching the n-type semiconductor layer provided between the plurality of light-emitting structures to expose the sacrificial layer disposed between the plurality of light-emitting structures;
forming an n-type contact layer contacting an upper surface of the n-type semiconductor layer;
removing the sacrificial layer disposed between the plurality of light-emitting structures to expose the adhesion layer;
separating a portion of the plurality of light-emitting structures from the first temporary substrate so as to be arranged a predetermined interval on a second temporary substrate; and
collectively attaching the light-emitting structures, which are arranged on the second temporary substrate, on a panel and removing the second temporary substrate.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the n-type contact layer has a first area contacting the lower surface of the n-type semiconductor layer and a second area contacting a side surface of the n-type semiconductor layer.

### Claim 3 (depends on 1)

The method according to claim 1, wherein a lower surface of the protection layer is disposed to contact the upper surface of the n-type contact layer.

### Claim 4 (depends on 1)

The method according to claim 1 wherein the upper surface of the n-type contact layer has a width equal to or greater than 70% of a width of the lower surface of the n-type semiconductor layer.